Register Region: A2W (`0x7e102000`)

Info

Name	Value
description	`Clock manager PLL control`
base	`0x7e102000`
id	`0x00613277`
password	`0x5a000000`

Registers

Register Name	Address	Type	Width	Mask	Reset
A2W_PLLA_DIG0	`0x7e102000`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_DIG1	`0x7e102004`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLA_DIG2	`0x7e102008`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLA_DIG3	`0x7e10200c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLA_ANA0	`0x7e102010`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_ANA1	`0x7e102014`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLA_ANA2	`0x7e102018`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_ANA3	`0x7e10201c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLC_DIG0	`0x7e102020`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_DIG1	`0x7e102024`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLC_DIG2	`0x7e102028`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLC_DIG3	`0x7e10202c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLC_ANA0	`0x7e102030`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_ANA1	`0x7e102034`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLC_ANA2	`0x7e102038`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_ANA3	`0x7e10203c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLD_DIG0	`0x7e102040`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_DIG1	`0x7e102044`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLD_DIG2	`0x7e102048`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLD_DIG3	`0x7e10204c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLD_ANA0	`0x7e102050`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_ANA1	`0x7e102054`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLD_ANA2	`0x7e102058`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_ANA3	`0x7e10205c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLH_DIG0	`0x7e102060`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_DIG1	`0x7e102064`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_DIG2	`0x7e102068`	RW	24	`0x00ffffff`	`0x000000aa`
A2W_PLLH_DIG3	`0x7e10206c`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_ANA0	`0x7e102070`	RW	24	`0x00ffffff`	`0x00d80000`
A2W_PLLH_ANA1	`0x7e102074`	RW	24	`0x00ffffff`	`0x00000014`
A2W_PLLH_ANA2	`0x7e102078`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_ANA3	`0x7e10207c`	RW	24	`0x00ffffff`	`0000000000`
A2W_HDMI_CTL0	`0x7e102080`	RW	24	`0x00ffffff`	`0x00470238`
A2W_HDMI_CTL1	`0x7e102084`	RW	24	`0x00ffffff`	`0x00011c00`
A2W_HDMI_CTL2	`0x7e102088`	RW	24	`0x00ffffff`	`0x0018048e`
A2W_HDMI_CTL3	`0x7e10208c`	RW	24	`0x00ffffff`	`0x00000040`
A2W_XOSC0	`0x7e102090`	RW	24	`0x00ffffff`	`0x00820080`
A2W_XOSC1	`0x7e102094`	RW	24	`0x00ffffff`	`0x00000006`
A2W_SMPS_CTLA0	`0x7e1020a0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLA1	`0x7e1020a4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLA2	`0x7e1020a8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB0	`0x7e1020b0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB1	`0x7e1020b4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB2	`0x7e1020b8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC0	`0x7e1020c0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC1	`0x7e1020c4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC2	`0x7e1020c8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC3	`0x7e1020cc`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_LDO0	`0x7e1020d0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_LDO1	`0x7e1020d4`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_DIG0	`0x7e1020e0`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_DIG1	`0x7e1020e4`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLB_DIG2	`0x7e1020e8`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLB_DIG3	`0x7e1020ec`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLB_ANA0	`0x7e1020f0`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_ANA1	`0x7e1020f4`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLB_ANA2	`0x7e1020f8`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_ANA3	`0x7e1020fc`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLA_CTRL	`0x7e102100`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLA_ANA_SSCS	`0x7e102110`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLC_CTRL	`0x7e102120`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLC_ANA_SSCS	`0x7e102130`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLD_CTRL	`0x7e102140`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLD_ANA_SSCS	`0x7e102150`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLH_CTRL	`0x7e102160`	RW	18	`0x000370ff`	`0x00010000`
A2W_HDMI_CTL_RCAL	`0x7e102180`	RW	17	`0x00011f33`	`0x00010000`
A2W_XOSC_CTRL	`0x7e102190`	RW	20	`0x000ff0ff`	`0000000000`
A2W_SMPS_A_MODE	`0x7e1021a0`	RW	1	`0x00000001`	`0000000000`
A2W_SMPS_B_STAT	`0x7e1021b0`	RW	13	`0x0000111f`	`0000000000`
A2W_SMPS_C_CLK	`0x7e1021c0`	RW	4	`0x0000000f`	`0000000000`
A2W_SMPS_L_SPV	`0x7e1021d0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_CTRL	`0x7e1021e0`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLB_ANA_SSCS	`0x7e1021f0`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLA_FRAC	`0x7e102200`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLA_ANA_SSCL	`0x7e102210`	RW	22	`0x003fffff`	`0000000000`
A2W_PLLC_FRAC	`0x7e102220`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLC_ANA_SSCL	`0x7e102230`	RW	22	`0x003fffff`	`0000000000`
A2W_PLLD_FRAC	`0x7e102240`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLD_ANA_SSCL	`0x7e102250`	RW	22	`0x003fffff`	`0000000000`
A2W_PLLH_FRAC	`0x7e102260`	RW	20	`0x000fffff`	`0000000000`
A2W_HDMI_CTL_HFEN	`0x7e102280`	RW	1	`0x00000001`	`0000000000`
A2W_XOSC_CPR	`0x7e102290`	RW	5	`0x00000013`	`0000000000`
A2W_SMPS_A_VOLTS	`0x7e1022a0`	RW	5	`0x0000001f`	`0000000000`
A2W_SMPS_C_CTL	`0x7e1022c0`	RW	2	`0x00000003`	`0000000000`
A2W_SMPS_L_SPA	`0x7e1022d0`	RW	10	`0x000003ff`	`0000000000`
A2W_PLLB_FRAC	`0x7e1022e0`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLB_ANA_SSCL	`0x7e1022f0`	RW	22	`0x003fffff`	`0000000000`
A2W_PLLA_DSI0	`0x7e102300`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_KAIP	`0x7e102310`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLC_CORE2	`0x7e102320`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_KAIP	`0x7e102330`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLD_DSI0	`0x7e102340`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_KAIP	`0x7e102350`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLH_AUX	`0x7e102360`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLH_ANA_KAIP	`0x7e102370`	RW	11	`0x0000077f`	`0x0000033a`
A2W_XOSC_BIAS	`0x7e102390`	RW	5	`0x0000001f`	`0x00000018`
A2W_SMPS_A_GAIN	`0x7e1023a0`	RW	3	`0x00000007`	`0000000000`
A2W_SMPS_L_SCV	`0x7e1023d0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_ARM	`0x7e1023e0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_KAIP	`0x7e1023f0`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLA_CORE	`0x7e102400`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_STAT	`0x7e102410`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLC_CORE1	`0x7e102420`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_STAT	`0x7e102430`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLD_CORE	`0x7e102440`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_STAT	`0x7e102450`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLH_RCAL	`0x7e102460`	RW	10	`0x000003ff`	`0x00000100`
A2W_XOSC_PWR	`0x7e102490`	RW	3	`0x00000007`	`0x00000004`
A2W_SMPS_L_SCA	`0x7e1024d0`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLB_SP0	`0x7e1024e0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_STAT	`0x7e1024f0`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLA_PER	`0x7e102500`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_SCTL	`0x7e102510`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLC_PER	`0x7e102520`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_SCTL	`0x7e102530`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLD_PER	`0x7e102540`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_SCTL	`0x7e102550`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLH_PIX	`0x7e102560`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLH_ANA_SCTL	`0x7e102570`	RW	5	`0x0000001f`	`0000000000`
A2W_SMPS_L_SIV	`0x7e1025d0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_SP1	`0x7e1025e0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_SCTL	`0x7e1025f0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLA_CCP2	`0x7e102600`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_VCO	`0x7e102610`	RW	1	`0x00000001`	`0000000000`
A2W_PLLC_CORE0	`0x7e102620`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_VCO	`0x7e102630`	RW	1	`0x00000001`	`0000000000`
A2W_PLLD_DSI1	`0x7e102640`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_VCO	`0x7e102650`	RW	1	`0x00000001`	`0000000000`
A2W_PLLH_ANA_STAT	`0x7e102660`	RW	21	`0x001f1fff`	`0000000000`
A2W_PLLH_ANA_VCO	`0x7e102670`	RW	1	`0x00000001`	`0000000000`
A2W_SMPS_L_SIA	`0x7e1026d0`	RW	10	`0x000003ff`	`0000000000`
A2W_PLLB_SP2	`0x7e1026e0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_VCO	`0x7e1026f0`	RW	1	`0x00000001`	`0000000000`
A2W_PLLA_DIG0R	`0x7e102800`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_DIG1R	`0x7e102804`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLA_DIG2R	`0x7e102808`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLA_DIG3R	`0x7e10280c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLA_ANA0R	`0x7e102810`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_ANA1R	`0x7e102814`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLA_ANA2R	`0x7e102818`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLA_ANA3R	`0x7e10281c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLC_DIG0R	`0x7e102820`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_DIG1R	`0x7e102824`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLC_DIG2R	`0x7e102828`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLC_DIG3R	`0x7e10282c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLC_ANA0R	`0x7e102830`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_ANA1R	`0x7e102834`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLC_ANA2R	`0x7e102838`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLC_ANA3R	`0x7e10283c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLD_DIG0R	`0x7e102840`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_DIG1R	`0x7e102844`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLD_DIG2R	`0x7e102848`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLD_DIG3R	`0x7e10284c`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLD_ANA0R	`0x7e102850`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_ANA1R	`0x7e102854`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLD_ANA2R	`0x7e102858`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLD_ANA3R	`0x7e10285c`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLH_DIG0R	`0x7e102860`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_DIG1R	`0x7e102864`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_DIG2R	`0x7e102868`	RW	24	`0x00ffffff`	`0x000000aa`
A2W_PLLH_DIG3R	`0x7e10286c`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_ANA0R	`0x7e102870`	RW	24	`0x00ffffff`	`0x00d80000`
A2W_PLLH_ANA1R	`0x7e102874`	RW	24	`0x00ffffff`	`0x00000014`
A2W_PLLH_ANA2R	`0x7e102878`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLH_ANA3R	`0x7e10287c`	RW	24	`0x00ffffff`	`0000000000`
A2W_HDMI_CTL0R	`0x7e102880`	RW	24	`0x00ffffff`	`0x00470238`
A2W_HDMI_CTL1R	`0x7e102884`	RW	24	`0x00ffffff`	`0x00011c00`
A2W_HDMI_CTL2R	`0x7e102888`	RW	24	`0x00ffffff`	`0x0018048e`
A2W_HDMI_CTL3R	`0x7e10288c`	RW	24	`0x00ffffff`	`0x00000040`
A2W_XOSC0R	`0x7e102890`	RW	24	`0x00ffffff`	`0x00820080`
A2W_XOSC1R	`0x7e102894`	RW	24	`0x00ffffff`	`0x00000006`
A2W_SMPS_CTLA0R	`0x7e1028a0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLA1R	`0x7e1028a4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLA2R	`0x7e1028a8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB0R	`0x7e1028b0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB1R	`0x7e1028b4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLB2R	`0x7e1028b8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC0R	`0x7e1028c0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC1R	`0x7e1028c4`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC2R	`0x7e1028c8`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_CTLC3R	`0x7e1028cc`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_LDO0R	`0x7e1028d0`	RW	24	`0x00ffffff`	`0000000000`
A2W_SMPS_LDO1R	`0x7e1028d4`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_DIG0R	`0x7e1028e0`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_DIG1R	`0x7e1028e4`	RW	24	`0x00ffffff`	`0x00004000`
A2W_PLLB_DIG2R	`0x7e1028e8`	RW	24	`0x00ffffff`	`0x00100401`
A2W_PLLB_DIG3R	`0x7e1028ec`	RW	24	`0x00ffffff`	`0x00000004`
A2W_PLLB_ANA0R	`0x7e1028f0`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_ANA1R	`0x7e1028f4`	RW	24	`0x00ffffff`	`0x001d0000`
A2W_PLLB_ANA2R	`0x7e1028f8`	RW	24	`0x00ffffff`	`0000000000`
A2W_PLLB_ANA3R	`0x7e1028fc`	RW	24	`0x00ffffff`	`0x00000180`
A2W_PLLA_CTRLR	`0x7e102900`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLA_ANA_SSCSR	`0x7e102910`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLC_CTRLR	`0x7e102920`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLC_ANA_SSCSR	`0x7e102930`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLD_CTRLR	`0x7e102940`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLD_ANA_SSCSR	`0x7e102950`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLH_CTRLR	`0x7e102960`	RW	18	`0x000370ff`	`0x00010000`
A2W_HDMI_CTL_RCALR	`0x7e102980`	RW	17	`0x00011f33`	`0x00010000`
A2W_XOSC_CTRLR	`0x7e102990`	RW	8	`0x000000ff`	`0000000000`
A2W_SMPS_A_MODER	`0x7e1029a0`	RW	1	`0x00000001`	`0000000000`
A2W_SMPS_B_STATR	`0x7e1029b0`	RW	13	`0x0000111f`	`0000000000`
A2W_SMPS_C_CLKR	`0x7e1029c0`	RW	4	`0x0000000f`	`0000000000`
A2W_SMPS_L_SPVR	`0x7e1029d0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_CTRLR	`0x7e1029e0`	RW	18	`0x000373ff`	`0x00010000`
A2W_PLLB_ANA_SSCSR	`0x7e1029f0`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLA_FRACR	`0x7e102a00`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLA_ANA_SSCLR	`0x7e102a10`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLC_FRACR	`0x7e102a20`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLC_ANA_SSCLR	`0x7e102a30`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLD_FRACR	`0x7e102a40`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLD_ANA_SSCLR	`0x7e102a50`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLH_FRACR	`0x7e102a60`	RW	20	`0x000fffff`	`0000000000`
A2W_HDMI_CTL_HFENR	`0x7e102a80`	RW	1	`0x00000001`	`0000000000`
A2W_XOSC_CPRR	`0x7e102a90`	RW	5	`0x00000013`	`0000000000`
A2W_SMPS_A_VOLTSR	`0x7e102aa0`	RW	5	`0x0000001f`	`0000000000`
A2W_SMPS_C_CTLR	`0x7e102ac0`	RW	2	`0x00000003`	`0000000000`
A2W_SMPS_L_SPAR	`0x7e102ad0`	RW	10	`0x000003ff`	`0000000000`
A2W_PLLB_FRACR	`0x7e102ae0`	RW	20	`0x000fffff`	`0000000000`
A2W_PLLB_ANA_SSCLR	`0x7e102af0`	RW	17	`0x0001ffff`	`0000000000`
A2W_PLLA_DSI0R	`0x7e102b00`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_KAIPR	`0x7e102b10`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLC_CORE2R	`0x7e102b20`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_KAIPR	`0x7e102b30`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLD_DSI0R	`0x7e102b40`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_KAIPR	`0x7e102b50`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLH_AUXR	`0x7e102b60`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLH_ANA_KAIPR	`0x7e102b70`	RW	11	`0x0000077f`	`0x0000033a`
A2W_XOSC_BIASR	`0x7e102b90`	RW	5	`0x0000001f`	`0x00000018`
A2W_SMPS_A_GAINR	`0x7e102ba0`	RW	3	`0x00000007`	`0000000000`
A2W_SMPS_L_SCVR	`0x7e102bd0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_ARMR	`0x7e102be0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_KAIPR	`0x7e102bf0`	RW	11	`0x0000077f`	`0x0000033a`
A2W_PLLA_CORER	`0x7e102c00`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_STATR	`0x7e102c10`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLC_CORE1R	`0x7e102c20`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_STATR	`0x7e102c30`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLD_CORER	`0x7e102c40`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_STATR	`0x7e102c50`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLH_RCALR	`0x7e102c60`	RW	10	`0x000003ff`	`0x00000100`
A2W_XOSC_PWRR	`0x7e102c90`	RW	3	`0x00000007`	`0x00000004`
A2W_SMPS_L_SCAR	`0x7e102cd0`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLB_SP0R	`0x7e102ce0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_STATR	`0x7e102cf0`	RW	12	`0x00000fff`	`0000000000`
A2W_PLLA_PERR	`0x7e102d00`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_SCTLR	`0x7e102d10`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLC_PERR	`0x7e102d20`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_SCTLR	`0x7e102d30`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLD_PERR	`0x7e102d40`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_SCTLR	`0x7e102d50`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLH_PIXR	`0x7e102d60`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLH_ANA_SCTLR	`0x7e102d70`	RW	5	`0x0000001f`	`0000000000`
A2W_SMPS_L_SIVR	`0x7e102dd0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLB_SP1R	`0x7e102de0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_SCTLR	`0x7e102df0`	RW	5	`0x0000001f`	`0000000000`
A2W_PLLA_CCP2R	`0x7e102e00`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLA_ANA_VCOR	`0x7e102e10`	RW	1	`0x00000001`	`0000000000`
A2W_PLLC_CORE0R	`0x7e102e20`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLC_ANA_VCOR	`0x7e102e30`	RW	1	`0x00000001`	`0000000000`
A2W_PLLD_DSI1R	`0x7e102e40`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLD_ANA_VCOR	`0x7e102e50`	RW	1	`0x00000001`	`0000000000`
A2W_PLLH_ANA_STATR	`0x7e102e60`	RW	21	`0x001f1fff`	`0000000000`
A2W_PLLH_ANA_VCOR	`0x7e102e70`	RW	1	`0x00000001`	`0000000000`
A2W_SMPS_L_SIAR	`0x7e102ed0`	RW	10	`0x000003ff`	`0000000000`
A2W_PLLB_SP2R	`0x7e102ee0`	RW	10	`0x000003ff`	`0x00000100`
A2W_PLLB_ANA_VCOR	`0x7e102ef0`	RW	1	`0x00000001`	`0000000000`
A2W_PLLA_MULTI	`0x7e102f00`	RW	0	`0000000000`	`0000000000`
A2W_PLLA_ANA_MULTI	`0x7e102f10`	RW	0	`0000000000`	`0000000000`
A2W_PLLC_MULTI	`0x7e102f20`	RW	0	`0000000000`	`0000000000`
A2W_PLLC_ANA_MULTI	`0x7e102f30`	RW	0	`0000000000`	`0000000000`
A2W_PLLD_MULTI	`0x7e102f40`	RW	0	`0000000000`	`0000000000`
A2W_PLLD_ANA_MULTI	`0x7e102f50`	RW	0	`0000000000`	`0000000000`
A2W_PLLH_MULTI	`0x7e102f60`	RW	0	`0000000000`	`0000000000`
A2W_PLLH_ANA_MULTI	`0x7e102f70`	RW	0	`0000000000`	`0000000000`
A2W_HDMI_CTL_MULTI	`0x7e102f80`	RW	0	`0000000000`	`0000000000`
A2W_XOSC_MULTI	`0x7e102f90`	RW	0	`0000000000`	`0000000000`
A2W_SMPS_A_MULTI	`0x7e102fa0`	RW	0	`0000000000`	`0000000000`
A2W_SMPS_B_MULTI	`0x7e102fb0`	RW	0	`0000000000`	`0000000000`
A2W_SMPS_C_MULTI	`0x7e102fc0`	RW	0	`0000000000`	`0000000000`
A2W_SMPS_L_MULTI	`0x7e102fd0`	RW	0	`0000000000`	`0000000000`
A2W_PLLB_MULTI	`0x7e102fe0`	RW	0	`0000000000`	`0000000000`
A2W_PLLB_ANA_MULTI	`0x7e102ff0`	RW	0	`0000000000`	`0000000000`

Register info

A2W_PLLA_CTRL

Address: `0x7e102100`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_CTRL_NDIV	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
A2W_PLLA_CTRL_PDIV	12	14	`0x00007000`	`0xffff8fff`	`0x0`
missing definiton	15	15	`NA`	`NA`	`NA`
A2W_PLLA_CTRL_PWRDN	16	16	`0x00010000`	`0xfffeffff`	`0x1`
A2W_PLLA_CTRL_PRSTN	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLA_ANA_SSCS

Address: `0x7e102110`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_SSCS_STEP	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
A2W_PLLA_ANA_SSCS_MODE	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLC_CTRL

Address: `0x7e102120`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_CTRL_NDIV	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
A2W_PLLC_CTRL_PDIV	12	14	`0x00007000`	`0xffff8fff`	`0x0`
missing definiton	15	15	`NA`	`NA`	`NA`
A2W_PLLC_CTRL_PWRDN	16	16	`0x00010000`	`0xfffeffff`	`0x1`
A2W_PLLC_CTRL_PRSTN	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLC_ANA_SSCS

Address: `0x7e102130`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_ANA_SSCS_STEP	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
A2W_PLLC_ANA_SSCS_MODE	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLD_CTRL

Address: `0x7e102140`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_CTRL_NDIV	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
A2W_PLLD_CTRL_PDIV	12	14	`0x00007000`	`0xffff8fff`	`0x0`
missing definiton	15	15	`NA`	`NA`	`NA`
A2W_PLLD_CTRL_PWRDN	16	16	`0x00010000`	`0xfffeffff`	`0x1`
A2W_PLLD_CTRL_PRSTN	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLD_ANA_SSCS

Address: `0x7e102150`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_ANA_SSCS_STEP	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
A2W_PLLD_ANA_SSCS_MODE	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLH_CTRL

Address: `0x7e102160`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_CTRL_NDIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
missing definiton	8	11	`NA`	`NA`	`NA`
A2W_PLLH_CTRL_PDIV	12	14	`0x00007000`	`0xffff8fff`	`0x0`
missing definiton	15	15	`NA`	`NA`	`NA`
A2W_PLLH_CTRL_PWRDN	16	16	`0x00010000`	`0xfffeffff`	`0x1`
A2W_PLLH_CTRL_PRSTN	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_HDMI_CTL_RCAL

Address: `0x7e102180`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_HDMI_CTL_RCAL_SELAVG	0	1	`0x00000003`	`0xfffffffc`	`0x0`
missing definiton	2	3	`NA`	`NA`	`NA`
A2W_HDMI_CTL_RCAL_SELDIV	4	5	`0x00000030`	`0xffffffcf`	`0x0`
missing definiton	6	7	`NA`	`NA`	`NA`
A2W_HDMI_CTL_RCAL_MANR	8	11	`0x00000f00`	`0xfffff0ff`	`0x0`
A2W_HDMI_CTL_RCAL_MANREN	12	12	`0x00001000`	`0xffffefff`	`0x0`
missing definiton	13	15	`NA`	`NA`	`NA`
A2W_HDMI_CTL_RCAL_RSTB	16	16	`0x00010000`	`0xfffeffff`	`0x1`

A2W_XOSC_CTRL

Address: `0x7e102190`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_XOSC_CTRL_PLLCEN	0	0	`0x00000001`	`0xfffffffe`	`0x0`
A2W_XOSC_CTRL_HDMIEN	1	1	`0x00000002`	`0xfffffffd`	`0x0`
A2W_XOSC_CTRL_USBEN	2	2	`0x00000004`	`0xfffffffb`	`0x0`
A2W_XOSC_CTRL_SMPSEN	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_XOSC_CTRL_DDREN	4	4	`0x00000010`	`0xffffffef`	`0x0`
A2W_XOSC_CTRL_PLLDEN	5	5	`0x00000020`	`0xffffffdf`	`0x0`
A2W_XOSC_CTRL_PLLAEN	6	6	`0x00000040`	`0xffffffbf`	`0x0`
A2W_XOSC_CTRL_PLLBEN	7	7	`0x00000080`	`0xffffff7f`	`0x0`
missing definiton	8	11	`NA`	`NA`	`NA`
A2W_XOSC_CTRL_PLLCOK	12	12	`0x00001000`	`0xffffefff`	`0x0`
A2W_XOSC_CTRL_HDMIOK	13	13	`0x00002000`	`0xffffdfff`	`0x0`
A2W_XOSC_CTRL_USBOK	14	14	`0x00004000`	`0xffffbfff`	`0x0`
A2W_XOSC_CTRL_SMPSOK	15	15	`0x00008000`	`0xffff7fff`	`0x0`
A2W_XOSC_CTRL_DDROK	16	16	`0x00010000`	`0xfffeffff`	`0x0`
A2W_XOSC_CTRL_PLLDOK	17	17	`0x00020000`	`0xfffdffff`	`0x0`
A2W_XOSC_CTRL_PLLAOK	18	18	`0x00040000`	`0xfffbffff`	`0x0`
A2W_XOSC_CTRL_PLLBOK	19	19	`0x00080000`	`0xfff7ffff`	`0x0`

A2W_SMPS_A_MODE

Address: `0x7e1021a0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_A_MODE_BSTPWMB	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_SMPS_B_STAT

Address: `0x7e1021b0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_B_STAT_VOLTS	0	4	`0x0000001f`	`0xffffffe0`	`0x0`
missing definiton	5	7	`NA`	`NA`	`NA`
A2W_SMPS_B_STAT_BSTPWMB	8	8	`0x00000100`	`0xfffffeff`	`0x0`
missing definiton	9	11	`NA`	`NA`	`NA`
A2W_SMPS_B_STAT_POK	12	12	`0x00001000`	`0xffffefff`	`0x0`

A2W_SMPS_C_CLK

Address: `0x7e1021c0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_C_CLK_OSCDIV	0	1	`0x00000003`	`0xfffffffc`	`0x0`
A2W_SMPS_C_CLK_USEOSC	2	2	`0x00000004`	`0xfffffffb`	`0x0`
A2W_SMPS_C_CLK_TDEN	3	3	`0x00000008`	`0xfffffff7`	`0x0`

A2W_SMPS_L_SPV

Address: `0x7e1021d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SPV_VOLTS	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_CTRL

Address: `0x7e1021e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_CTRL_NDIV	0	9	`0x000003ff`	`0xfffffc00`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
A2W_PLLB_CTRL_PDIV	12	14	`0x00007000`	`0xffff8fff`	`0x0`
missing definiton	15	15	`NA`	`NA`	`NA`
A2W_PLLB_CTRL_PWRDN	16	16	`0x00010000`	`0xfffeffff`	`0x1`
A2W_PLLB_CTRL_PRSTN	17	17	`0x00020000`	`0xfffdffff`	`0x0`

A2W_PLLB_ANA_SSCS

Address: `0x7e1021f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_SSCS_STEP	0	15	`0x0000ffff`	`0xffff0000`	`0x0`
A2W_PLLB_ANA_SSCS_MODE	16	16	`0x00010000`	`0xfffeffff`	`0x0`

A2W_PLLA_FRAC

Address: `0x7e102200`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_FRAC_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLA_ANA_SSCL

Address: `0x7e102210`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_SSCL_LIMIT	0	21	`0x003fffff`	`0xffc00000`	`0x0`

A2W_PLLC_FRAC

Address: `0x7e102220`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_FRAC_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLD_FRAC

Address: `0x7e102240`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_FRAC_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLH_FRAC

Address: `0x7e102260`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_FRAC_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_HDMI_CTL_HFEN

Address: `0x7e102280`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_HDMI_CTL_HFEN_HFEN	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_XOSC_CPR

Address: `0x7e102290`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_XOSC_CPR_DIV	0	1	`0x00000003`	`0xfffffffc`	`0x0`
missing definiton	2	3	`NA`	`NA`	`NA`
A2W_XOSC_CPR_CPR1	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_SMPS_A_VOLTS

Address: `0x7e1022a0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_A_VOLTS_VOLTS	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_SMPS_C_CTL

Address: `0x7e1022c0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_C_CTL_CTRLEN	0	0	`0x00000001`	`0xfffffffe`	`0x0`
A2W_SMPS_C_CTL_UPEN	1	1	`0x00000002`	`0xfffffffd`	`0x0`

A2W_SMPS_L_SPA

Address: `0x7e1022d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SPA_ANA	0	9	`0x000003ff`	`0xfffffc00`	`0x0`

A2W_PLLB_FRAC

Address: `0x7e1022e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_FRAC_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

A2W_PLLB_ANA_SSCL

Address: `0x7e1022f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_SSCL_LIMIT	0	21	`0x003fffff`	`0xffc00000`	`0x0`

A2W_PLLA_DSI0

Address: `0x7e102300`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_DSI0_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLA_DSI0_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLA_DSI0_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_KAIP

Address: `0x7e102310`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_KAIP_KP	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
A2W_PLLA_ANA_KAIP_KI	4	6	`0x00000070`	`0xffffff8f`	`0x3`
missing definiton	7	7	`NA`	`NA`	`NA`
A2W_PLLA_ANA_KAIP_KA	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLC_CORE2

Address: `0x7e102320`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_CORE2_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLC_CORE2_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLC_CORE2_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_KAIP

Address: `0x7e102330`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_ANA_KAIP_KP	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
A2W_PLLC_ANA_KAIP_KI	4	6	`0x00000070`	`0xffffff8f`	`0x3`
missing definiton	7	7	`NA`	`NA`	`NA`
A2W_PLLC_ANA_KAIP_KA	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLD_DSI0

Address: `0x7e102340`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_DSI0_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLD_DSI0_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLD_DSI0_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_KAIP

Address: `0x7e102350`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_ANA_KAIP_KP	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
A2W_PLLD_ANA_KAIP_KI	4	6	`0x00000070`	`0xffffff8f`	`0x3`
missing definiton	7	7	`NA`	`NA`	`NA`
A2W_PLLD_ANA_KAIP_KA	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLH_AUX

Address: `0x7e102360`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_AUX_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLH_AUX_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLH_AUX_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLH_ANA_KAIP

Address: `0x7e102370`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_ANA_KAIP_KP	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
A2W_PLLH_ANA_KAIP_KI	4	6	`0x00000070`	`0xffffff8f`	`0x3`
missing definiton	7	7	`NA`	`NA`	`NA`
A2W_PLLH_ANA_KAIP_KA	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_XOSC_BIAS

Address: `0x7e102390`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_XOSC_BIAS_BIAS	0	3	`0x0000000f`	`0xfffffff0`	`0x8`
A2W_XOSC_BIAS_HIGHP	4	4	`0x00000010`	`0xffffffef`	`0x1`

A2W_SMPS_A_GAIN

Address: `0x7e1023a0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_A_GAIN_DIGGAIN	0	2	`0x00000007`	`0xfffffff8`	`0x0`

A2W_SMPS_L_SCV

Address: `0x7e1023d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SCV_VOLTS	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_ARM

Address: `0x7e1023e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ARM_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLB_ARM_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLB_ARM_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_KAIP

Address: `0x7e1023f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_KAIP_KP	0	3	`0x0000000f`	`0xfffffff0`	`0xa`
A2W_PLLB_ANA_KAIP_KI	4	6	`0x00000070`	`0xffffff8f`	`0x3`
missing definiton	7	7	`NA`	`NA`	`NA`
A2W_PLLB_ANA_KAIP_KA	8	10	`0x00000700`	`0xfffff8ff`	`0x3`

A2W_PLLA_CORE

Address: `0x7e102400`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_CORE_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLA_CORE_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLA_CORE_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_STAT

Address: `0x7e102410`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_STAT_DATA	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLC_CORE1

Address: `0x7e102420`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_CORE1_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLC_CORE1_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLC_CORE1_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_STAT

Address: `0x7e102430`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_ANA_STAT_DATA	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLD_CORE

Address: `0x7e102440`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_CORE_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLD_CORE_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLD_CORE_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_STAT

Address: `0x7e102450`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_ANA_STAT_DATA	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLH_RCAL

Address: `0x7e102460`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_RCAL_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLH_RCAL_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLH_RCAL_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_XOSC_PWR

Address: `0x7e102490`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_XOSC_PWR_BYPASS	0	0	`0x00000001`	`0xfffffffe`	`0x0`
A2W_XOSC_PWR_PWRDN	1	1	`0x00000002`	`0xfffffffd`	`0x0`
A2W_XOSC_PWR_RSTB	2	2	`0x00000004`	`0xfffffffb`	`0x1`

A2W_SMPS_L_SCA

Address: `0x7e1024d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SCA_ANA	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLB_SP0

Address: `0x7e1024e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_SP0_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLB_SP0_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLB_SP0_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_STAT

Address: `0x7e1024f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_STAT_DATA	0	11	`0x00000fff`	`0xfffff000`	`0x0`

A2W_PLLA_PER

Address: `0x7e102500`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_PER_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLA_PER_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLA_PER_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_SCTL

Address: `0x7e102510`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_SCTL_SEL	0	2	`0x00000007`	`0xfffffff8`	`0x0`
A2W_PLLA_ANA_SCTL_UPDATE	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_PLLA_ANA_SCTL_RESET	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLC_PER

Address: `0x7e102520`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_PER_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLC_PER_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLC_PER_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_SCTL

Address: `0x7e102530`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_ANA_SCTL_SEL	0	2	`0x00000007`	`0xfffffff8`	`0x0`
A2W_PLLC_ANA_SCTL_UPDATE	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_PLLC_ANA_SCTL_RESET	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLD_PER

Address: `0x7e102540`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_PER_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLD_PER_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLD_PER_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_SCTL

Address: `0x7e102550`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_ANA_SCTL_SEL	0	2	`0x00000007`	`0xfffffff8`	`0x0`
A2W_PLLD_ANA_SCTL_UPDATE	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_PLLD_ANA_SCTL_RESET	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLH_PIX

Address: `0x7e102560`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_PIX_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLH_PIX_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLH_PIX_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLH_ANA_SCTL

Address: `0x7e102570`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_ANA_SCTL_SEL	0	2	`0x00000007`	`0xfffffff8`	`0x0`
A2W_PLLH_ANA_SCTL_UPDATE	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_PLLH_ANA_SCTL_RESET	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_SMPS_L_SIV

Address: `0x7e1025d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SIV_VOLTS	0	4	`0x0000001f`	`0xffffffe0`	`0x0`

A2W_PLLB_SP1

Address: `0x7e1025e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_SP1_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLB_SP1_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLB_SP1_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_SCTL

Address: `0x7e1025f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_SCTL_SEL	0	2	`0x00000007`	`0xfffffff8`	`0x0`
A2W_PLLB_ANA_SCTL_UPDATE	3	3	`0x00000008`	`0xfffffff7`	`0x0`
A2W_PLLB_ANA_SCTL_RESET	4	4	`0x00000010`	`0xffffffef`	`0x0`

A2W_PLLA_CCP2

Address: `0x7e102600`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_CCP2_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLA_CCP2_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLA_CCP2_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLA_ANA_VCO

Address: `0x7e102610`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLA_ANA_VCO_RANGE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLC_CORE0

Address: `0x7e102620`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_CORE0_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLC_CORE0_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLC_CORE0_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLC_ANA_VCO

Address: `0x7e102630`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLC_ANA_VCO_RANGE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLD_DSI1

Address: `0x7e102640`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_DSI1_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLD_DSI1_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLD_DSI1_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLD_ANA_VCO

Address: `0x7e102650`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLD_ANA_VCO_RANGE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_PLLH_ANA_STAT

Address: `0x7e102660`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_ANA_STAT_DATA	0	11	`0x00000fff`	`0xfffff000`	`0x0`
A2W_PLLH_ANA_STAT_RCALDONE	12	12	`0x00001000`	`0xffffefff`	`0x0`
missing definiton	13	15	`NA`	`NA`	`NA`
A2W_PLLH_ANA_STAT_RCALCODE	16	19	`0x000f0000`	`0xfff0ffff`	`0x0`
A2W_PLLH_ANA_STAT_CNTLENB	20	20	`0x00100000`	`0xffefffff`	`0x0`

A2W_PLLH_ANA_VCO

Address: `0x7e102670`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLH_ANA_VCO_RANGE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

A2W_SMPS_L_SIA

Address: `0x7e1026d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_SMPS_L_SIA_ANA	0	9	`0x000003ff`	`0xfffffc00`	`0x0`

A2W_PLLB_SP2

Address: `0x7e1026e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_SP2_DIV	0	7	`0x000000ff`	`0xffffff00`	`0x0`
A2W_PLLB_SP2_CHENB	8	8	`0x00000100`	`0xfffffeff`	`0x1`
A2W_PLLB_SP2_BYPEN	9	9	`0x00000200`	`0xfffffdff`	`0x0`

A2W_PLLB_ANA_VCO

Address: `0x7e1026f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
A2W_PLLB_ANA_VCO_RANGE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

<< RPi Registers Index

Register Region: A2W (0x7e102000)

Info

Registers

Register info

Address: 0x7e102100

Address: 0x7e102110

Address: 0x7e102120

Address: 0x7e102130

Address: 0x7e102140

Address: 0x7e102150

Address: 0x7e102160

Address: 0x7e102180

Address: 0x7e102190

Address: 0x7e1021a0

Address: 0x7e1021b0

Address: 0x7e1021c0

Address: 0x7e1021d0

Address: 0x7e1021e0

Address: 0x7e1021f0

Address: 0x7e102200

Address: 0x7e102210

Address: 0x7e102220

Address: 0x7e102240

Address: 0x7e102260

Address: 0x7e102280

Address: 0x7e102290

Address: 0x7e1022a0

Address: 0x7e1022c0

Address: 0x7e1022d0

Address: 0x7e1022e0

Address: 0x7e1022f0

Address: 0x7e102300

Address: 0x7e102310

Address: 0x7e102320

Address: 0x7e102330

Address: 0x7e102340

Address: 0x7e102350

Address: 0x7e102360

Address: 0x7e102370

Address: 0x7e102390

Address: 0x7e1023a0

Address: 0x7e1023d0

Address: 0x7e1023e0

Address: 0x7e1023f0

Address: 0x7e102400

Address: 0x7e102410

Address: 0x7e102420

Address: 0x7e102430

Address: 0x7e102440

Address: 0x7e102450

Address: 0x7e102460

Address: 0x7e102490

Address: 0x7e1024d0

Address: 0x7e1024e0

Address: 0x7e1024f0

Address: 0x7e102500

Address: 0x7e102510

Address: 0x7e102520

Address: 0x7e102530

Address: 0x7e102540

Address: 0x7e102550

Address: 0x7e102560

Address: 0x7e102570

Address: 0x7e1025d0

Address: 0x7e1025e0

Address: 0x7e1025f0

Address: 0x7e102600

Address: 0x7e102610

Address: 0x7e102620

Address: 0x7e102630

Address: 0x7e102640

Address: 0x7e102650

Address: 0x7e102660

Address: 0x7e102670

Address: 0x7e1026d0

Address: 0x7e1026e0

Address: 0x7e1026f0

Register Region: A2W (`0x7e102000`)

Address: `0x7e102100`

Address: `0x7e102110`

Address: `0x7e102120`

Address: `0x7e102130`

Address: `0x7e102140`

Address: `0x7e102150`

Address: `0x7e102160`

Address: `0x7e102180`

Address: `0x7e102190`

Address: `0x7e1021a0`

Address: `0x7e1021b0`

Address: `0x7e1021c0`

Address: `0x7e1021d0`

Address: `0x7e1021e0`

Address: `0x7e1021f0`

Address: `0x7e102200`

Address: `0x7e102210`

Address: `0x7e102220`

Address: `0x7e102240`

Address: `0x7e102260`

Address: `0x7e102280`

Address: `0x7e102290`

Address: `0x7e1022a0`

Address: `0x7e1022c0`

Address: `0x7e1022d0`

Address: `0x7e1022e0`

Address: `0x7e1022f0`

Address: `0x7e102300`

Address: `0x7e102310`

Address: `0x7e102320`

Address: `0x7e102330`

Address: `0x7e102340`

Address: `0x7e102350`

Address: `0x7e102360`

Address: `0x7e102370`

Address: `0x7e102390`

Address: `0x7e1023a0`

Address: `0x7e1023d0`

Address: `0x7e1023e0`

Address: `0x7e1023f0`

Address: `0x7e102400`

Address: `0x7e102410`

Address: `0x7e102420`

Address: `0x7e102430`

Address: `0x7e102440`

Address: `0x7e102450`

Address: `0x7e102460`

Address: `0x7e102490`

Address: `0x7e1024d0`

Address: `0x7e1024e0`

Address: `0x7e1024f0`

Address: `0x7e102500`

Address: `0x7e102510`

Address: `0x7e102520`

Address: `0x7e102530`

Address: `0x7e102540`

Address: `0x7e102550`

Address: `0x7e102560`

Address: `0x7e102570`

Address: `0x7e1025d0`

Address: `0x7e1025e0`

Address: `0x7e1025f0`

Address: `0x7e102600`

Address: `0x7e102610`

Address: `0x7e102620`

Address: `0x7e102630`

Address: `0x7e102640`

Address: `0x7e102650`

Address: `0x7e102660`

Address: `0x7e102670`

Address: `0x7e1026d0`

Address: `0x7e1026e0`

Address: `0x7e1026f0`