Register Region: CM (`0x7e101000`)

Info

Name	Value
description	`Clock manager`
base	`0x7e101000`
id	`0x0000636d`
password	`0x5a000000`

Registers

Register Name	Address	Type	Width	Mask	Reset
CM_GNRICCTL	`0x7e101000`	RW	20	`0x000fffff`	`0000000000`
CM_GNRICDIV	`0x7e101004`	RW	24	`0x00ffffff`	`0000000000`
CM_VPUCTL	`0x7e101008`	RW	10	`0x000003cf`	`0x00000041`
CM_VPUDIV	`0x7e10100c`	RW	24	`0x00fffff0`	`0x00001000`
CM_SYSCTL	`0x7e101010`	RW	7	`0x00000040`	`0x00000040`
CM_SYSDIV	`0x7e101014`	RO	13	`0x00001000`	`0x00001000`
CM_PERIACTL	`0x7e101018`	RW	7	`0x00000040`	`0x00000040`
CM_PERIADIV	`0x7e10101c`	RO	13	`0x00001000`	`0x00001000`
CM_PERIICTL	`0x7e101020`	RW	7	`0x00000040`	`0000000000`
CM_PERIIDIV	`0x7e101024`	RO	13	`0x00001000`	`0x00001000`
CM_H264CTL	`0x7e101028`	RW	10	`0x000003ff`	`0x00000040`
CM_H264DIV	`0x7e10102c`	RW	16	`0x0000fff0`	`0000000000`
CM_ISPCTL	`0x7e101030`	RW	10	`0x000003ff`	`0x00000040`
CM_ISPDIV	`0x7e101034`	RW	16	`0x0000fff0`	`0000000000`
CM_V3DCTL	`0x7e101038`	RW	10	`0x000003ff`	`0x00000040`
CM_V3DDIV	`0x7e10103c`	RW	16	`0x0000fff0`	`0000000000`
CM_CAM0CTL	`0x7e101040`	RW	10	`0x000003bf`	`0000000000`
CM_CAM0DIV	`0x7e101044`	RW	16	`0x0000fff0`	`0000000000`
CM_CAM1CTL	`0x7e101048`	RW	10	`0x000003bf`	`0000000000`
CM_CAM1DIV	`0x7e10104c`	RW	16	`0x0000fff0`	`0000000000`
CM_CCP2CTL	`0x7e101050`	RW	10	`0x00000397`	`0000000000`
CM_CCP2DIV	`0x7e101054`	RO	13	`0x00001000`	`0x00001000`
CM_DSI0ECTL	`0x7e101058`	RW	10	`0x000003bf`	`0000000000`
CM_DSI0EDIV	`0x7e10105c`	RW	16	`0x0000fff0`	`0000000000`
CM_DSI0PCTL	`0x7e101060`	RW	10	`0x0000039f`	`0000000000`
CM_DSI0PDIV	`0x7e101064`	RO	13	`0x00001000`	`0x00001000`
CM_DPICTL	`0x7e101068`	RW	10	`0x000003bf`	`0000000000`
CM_DPIDIV	`0x7e10106c`	RW	16	`0x0000fff0`	`0000000000`
CM_GP0CTL	`0x7e101070`	RW	11	`0x000007bf`	`0x00000200`
CM_GP0DIV	`0x7e101074`	RW	24	`0x00ffffff`	`0000000000`
CM_GP1CTL	`0x7e101078`	RW	11	`0x000007bf`	`0x00000200`
CM_GP1DIV	`0x7e10107c`	RW	24	`0x00ffffff`	`0000000000`
CM_GP2CTL	`0x7e101080`	RW	10	`0x000003bf`	`0000000000`
CM_GP2DIV	`0x7e101084`	RW	24	`0x00ffffff`	`0000000000`
CM_HSMCTL	`0x7e101088`	RW	10	`0x000003ff`	`0000000000`
CM_HSMDIV	`0x7e10108c`	RW	16	`0x0000fff0`	`0000000000`
CM_OTPCTL	`0x7e101090`	RW	10	`0x000003b3`	`0x00000011`
CM_OTPDIV	`0x7e101094`	RW	17	`0x0001f000`	`0x00004000`
CM_PCMCTL	`0x7e101098`	RW	11	`0x000007bf`	`0x00000200`
CM_PCMDIV	`0x7e10109c`	RW	24	`0x00ffffff`	`0000000000`
CM_PWMCTL	`0x7e1010a0`	RW	11	`0x000007bf`	`0x00000200`
CM_PWMDIV	`0x7e1010a4`	RW	24	`0x00ffffff`	`0000000000`
CM_SLIMCTL	`0x7e1010a8`	RW	11	`0x000007bf`	`0x00000200`
CM_SLIMDIV	`0x7e1010ac`	RW	24	`0x00ffffff`	`0000000000`
CM_SMICTL	`0x7e1010b0`	RW	10	`0x000003bf`	`0000000000`
CM_SMIDIV	`0x7e1010b4`	RW	16	`0x0000fff0`	`0000000000`
CM_TCNTCTL	`0x7e1010c0`	RW	14	`0x000030cf`	`0000000000`
CM_TCNTCNT	`0x7e1010c4`	RW	24	`0x00ffffff`	`0000000000`
CM_TECCTL	`0x7e1010c8`	RW	10	`0x000003b3`	`0000000000`
CM_TECDIV	`0x7e1010cc`	RW	18	`0x0003f000`	`0000000000`
CM_TD0CTL	`0x7e1010d0`	RW	13	`0x00001bff`	`0000000000`
CM_TD0DIV	`0x7e1010d4`	RW	24	`0x00ffffff`	`0000000000`
CM_TD1CTL	`0x7e1010d8`	RW	13	`0x00001bff`	`0000000000`
CM_TD1DIV	`0x7e1010dc`	RW	24	`0x00ffffff`	`0000000000`
CM_TSENSCTL	`0x7e1010e0`	RW	10	`0x000003b3`	`0000000000`
CM_TSENSDIV	`0x7e1010e4`	RW	17	`0x0001f000`	`0000000000`
CM_TIMERCTL	`0x7e1010e8`	RW	10	`0x000003b3`	`0000000000`
CM_TIMERDIV	`0x7e1010ec`	RW	18	`0x0003ffff`	`0000000000`
CM_UARTCTL	`0x7e1010f0`	RW	10	`0x000003bf`	`0000000000`
CM_UARTDIV	`0x7e1010f4`	RW	22	`0x003fffff`	`0000000000`
CM_VECCTL	`0x7e1010f8`	RW	10	`0x000003bf`	`0000000000`
CM_VECDIV	`0x7e1010fc`	RW	16	`0x0000f000`	`0000000000`
CM_OSCCOUNT	`0x7e101100`	RW	24	`0x00ffffff`	`0000000000`
CM_PLLA	`0x7e101104`	RW	10	`0x000003ff`	`0x00000300`
CM_PLLC	`0x7e101108`	RW	10	`0x000003ff`	`0x00000300`
CM_PLLD	`0x7e10110c`	RW	10	`0x000003ff`	`0x00000300`
CM_PLLH	`0x7e101110`	RW	10	`0x00000307`	`0x00000300`
CM_LOCK	`0x7e101114`	RW	13	`0x00001f1f`	`0000000000`
CM_EVENT	`0x7e101118`	RW	24	`0x00ffffff`	`0000000000`
CM_INTEN	`0x7e10111c`	RW	24	`0x00ffffff`	`0000000000`
CM_DSI0HSCK	`0x7e101120`	RW	1	`0x00000001`	`0000000000`
CM_CKSM	`0x7e101124`	RW	22	`0x003fffff`	`0000000000`
CM_OSCFREQI	`0x7e101128`	RW	8	`0x000000ff`	`0000000000`
CM_OSCFREQF	`0x7e10112c`	RW	20	`0x000fffff`	`0000000000`
CM_PLLTCTL	`0x7e101130`	RW	8	`0x000000a7`	`0000000000`
CM_PLLTCNT0	`0x7e101134`	RW	24	`0x00ffffff`	`0000000000`
CM_PLLTCNT1	`0x7e101138`	RW	24	`0x00ffffff`	`0000000000`
CM_PLLTCNT2	`0x7e10113c`	RW	24	`0x00ffffff`	`0000000000`
CM_PLLTCNT3	`0x7e101140`	RW	24	`0x00ffffff`	`0000000000`
CM_TDCLKEN	`0x7e101144`	RW	14	`0x00003fff`	`0000000000`
CM_BURSTCTL	`0x7e101148`	RW	8	`0x000000b0`	`0000000000`
CM_BURSTCNT	`0x7e10114c`	RW	24	`0x00ffffff`	`0000000000`
CM_DSI1ECTL	`0x7e101158`	RW	10	`0x000003bf`	`0000000000`
CM_DSI1EDIV	`0x7e10115c`	RW	16	`0x0000fff0`	`0000000000`
CM_DSI1PCTL	`0x7e101160`	RW	10	`0x0000039f`	`0000000000`
CM_DSI1PDIV	`0x7e101164`	RO	13	`0x00001000`	`0x00001000`
CM_DFTCTL	`0x7e101168`	RW	10	`0x000003bf`	`0000000000`
CM_DFTDIV	`0x7e10116c`	RW	17	`0x0001f000`	`0000000000`
CM_PLLB	`0x7e101170`	RW	10	`0x00000303`	`0x00000300`
CM_PULSECTL	`0x7e101190`	RW	10	`0x000003b3`	`0x00000011`
CM_PULSEDIV	`0x7e101194`	RW	24	`0x00fff000`	`0x0001b000`
CM_SDCCTL	`0x7e1011a8`	RW	18	`0x0003f3bf`	`0x00004000`
CM_SDCDIV	`0x7e1011ac`	RW	18	`0x0003f000`	`0000000000`
CM_ARMCTL	`0x7e1011b0`	RW	13	`0x000013bf`	`0x00000004`
CM_ARMDIV	`0x7e1011b4`	RO	13	`0x00001000`	`0x00001000`
CM_AVEOCTL	`0x7e1011b8`	RW	10	`0x000003bf`	`0000000000`
CM_AVEODIV	`0x7e1011bc`	RW	16	`0x0000f000`	`0000000000`
CM_EMMCCTL	`0x7e1011c0`	RW	10	`0x000003bf`	`0000000000`
CM_EMMCDIV	`0x7e1011c4`	RW	16	`0x0000fff0`	`0000000000`

Register info

CM_GNRICCTL

Address: `0x7e101000`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GNRICCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_GNRICCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_GNRICCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_GNRICCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_GNRICCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_GNRICCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_GNRICCTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x0`
CM_GNRICCTL_FLIP	11	11	`0x00000800`	`0xfffff7ff`	`0x0`

CM_GNRICDIV

Address: `0x7e101004`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GNRICDIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_VPUCTL

Address: `0x7e101008`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_VPUCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x1`
missing definiton	4	5	`NA`	`NA`	`NA`
CM_VPUCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`
CM_VPUCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_VPUCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_VPUCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_VPUDIV

Address: `0x7e10100c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_VPUDIV_DIV	4	23	`0x00fffff0`	`0xff00000f`	`0x100`

CM_SYSCTL

Address: `0x7e101010`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	5	`NA`	`NA`	`NA`
CM_SYSCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`

CM_SYSDIV

Address: `0x7e101014`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_SYSDIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_PERIACTL

Address: `0x7e101018`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	5	`NA`	`NA`	`NA`
CM_PERIACTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`

CM_PERIADIV

Address: `0x7e10101c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_PERIADIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_PERIICTL

Address: `0x7e101020`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	5	`NA`	`NA`	`NA`
CM_PERIICTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x0`

CM_PERIIDIV

Address: `0x7e101024`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_PERIIDIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_H264CTL

Address: `0x7e101028`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_H264CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_H264CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_H264CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_H264CTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`
CM_H264CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_H264CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_H264CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_H264DIV

Address: `0x7e10102c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_H264DIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_ISPCTL

Address: `0x7e101030`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_ISPCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_ISPCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_ISPCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_ISPCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`
CM_ISPCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_ISPCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_ISPCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_ISPDIV

Address: `0x7e101034`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_ISPDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_V3DCTL

Address: `0x7e101038`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_V3DCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_V3DCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_V3DCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_V3DCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x1`
CM_V3DCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_V3DCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_V3DCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_V3DDIV

Address: `0x7e10103c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_V3DDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CAM0CTL

Address: `0x7e101040`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_CAM0CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_CAM0CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_CAM0CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_CAM0CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_CAM0CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_CAM0CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CAM0DIV

Address: `0x7e101044`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_CAM0DIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CAM1CTL

Address: `0x7e101048`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_CAM1CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_CAM1CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_CAM1CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_CAM1CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_CAM1CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_CAM1CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CAM1DIV

Address: `0x7e10104c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_CAM1DIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_CCP2CTL

Address: `0x7e101050`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_CCP2CTL_SRC	0	2	`0x00000007`	`0xfffffff8`	`0x0`
missing definiton	3	3	`NA`	`NA`	`NA`
CM_CCP2CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
missing definiton	5	6	`NA`	`NA`	`NA`
CM_CCP2CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_CCP2CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_CCP2CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_CCP2DIV

Address: `0x7e101054`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_CCP2DIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DSI0ECTL

Address: `0x7e101058`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DSI0ECTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DSI0ECTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_DSI0ECTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_DSI0ECTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DSI0ECTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DSI0ECTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI0EDIV

Address: `0x7e10105c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_DSI0EDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_DSI0PCTL

Address: `0x7e101060`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DSI0PCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DSI0PCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
missing definiton	5	6	`NA`	`NA`	`NA`
CM_DSI0PCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DSI0PCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DSI0PCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI0PDIV

Address: `0x7e101064`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_DSI0PDIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DPICTL

Address: `0x7e101068`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DPICTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DPICTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_DPICTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_DPICTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DPICTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DPICTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DPIDIV

Address: `0x7e10106c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_DPIDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_GP0CTL

Address: `0x7e101070`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP0CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_GP0CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_GP0CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_GP0CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_GP0CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_GP0CTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_GP0DIV

Address: `0x7e101074`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP0DIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_GP1CTL

Address: `0x7e101078`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP1CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_GP1CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_GP1CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_GP1CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_GP1CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_GP1CTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_GP1DIV

Address: `0x7e10107c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP1DIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_GP2CTL

Address: `0x7e101080`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP2CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_GP2CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_GP2CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_GP2CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_GP2CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_GP2CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_GP2DIV

Address: `0x7e101084`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_GP2DIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_HSMCTL

Address: `0x7e101088`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_HSMCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_HSMCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_HSMCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_HSMCTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_HSMCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_HSMCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_HSMCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_HSMDIV

Address: `0x7e10108c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_HSMDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_OTPCTL

Address: `0x7e101090`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_OTPCTL_SRC	0	1	`0x00000003`	`0xfffffffc`	`0x1`
missing definiton	2	3	`NA`	`NA`	`NA`
CM_OTPCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x1`
CM_OTPCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_OTPCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_OTPCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_OTPCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_OTPDIV

Address: `0x7e101094`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_OTPDIV_DIV	12	16	`0x0001f000`	`0xfffe0fff`	`0x4`

CM_PCMCTL

Address: `0x7e101098`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PCMCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_PCMCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_PCMCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_PCMCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PCMCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_PCMCTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_PCMDIV

Address: `0x7e10109c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PCMDIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PWMCTL

Address: `0x7e1010a0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PWMCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_PWMCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_PWMCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_PWMCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PWMCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_PWMCTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_PWMDIV

Address: `0x7e1010a4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PWMDIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_SLIMCTL

Address: `0x7e1010a8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_SLIMCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_SLIMCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_SLIMCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_SLIMCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_SLIMCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_SLIMCTL_MASH	9	10	`0x00000600`	`0xfffff9ff`	`0x1`

CM_SLIMDIV

Address: `0x7e1010ac`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_SLIMDIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_SMICTL

Address: `0x7e1010b0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_SMICTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_SMICTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_SMICTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_SMICTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_SMICTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_SMICTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_SMIDIV

Address: `0x7e1010b4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_SMIDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_TCNTCTL

Address: `0x7e1010c0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TCNTCTL_SRC0	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
missing definiton	4	5	`NA`	`NA`	`NA`
CM_TCNTCTL_KILL	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_TCNTCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
missing definiton	8	11	`NA`	`NA`	`NA`
CM_TCNTCTL_SRC1	12	13	`0x00003000`	`0xffffcfff`	`0x0`

CM_TCNTCNT

Address: `0x7e1010c4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TCNTCNT_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TECCTL

Address: `0x7e1010c8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TECCTL_SRC	0	1	`0x00000003`	`0xfffffffc`	`0x0`
missing definiton	2	3	`NA`	`NA`	`NA`
CM_TECCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TECCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_TECCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TECCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TECCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TECDIV

Address: `0x7e1010cc`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_TECDIV_DIV	12	17	`0x0003f000`	`0xfffc0fff`	`0x0`

CM_TD0CTL

Address: `0x7e1010d0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TD0CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_TD0CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TD0CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_TD0CTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_TD0CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TD0CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TD0CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`
missing definiton	10	10	`NA`	`NA`	`NA`
CM_TD0CTL_FLIP	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_TD0CTL_STEP	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_TD0DIV

Address: `0x7e1010d4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TD0DIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TD1CTL

Address: `0x7e1010d8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TD1CTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_TD1CTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TD1CTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_TD1CTL_GATE	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_TD1CTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TD1CTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TD1CTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`
missing definiton	10	10	`NA`	`NA`	`NA`
CM_TD1CTL_FLIP	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_TD1CTL_STEP	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_TD1DIV

Address: `0x7e1010dc`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TD1DIV_DIV	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TSENSCTL

Address: `0x7e1010e0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TSENSCTL_SRC	0	1	`0x00000003`	`0xfffffffc`	`0x0`
missing definiton	2	3	`NA`	`NA`	`NA`
CM_TSENSCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TSENSCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_TSENSCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TSENSCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TSENSCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TSENSDIV

Address: `0x7e1010e4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_TSENSDIV_DIV	12	16	`0x0001f000`	`0xfffe0fff`	`0x0`

CM_TIMERCTL

Address: `0x7e1010e8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TIMERCTL_SRC	0	1	`0x00000003`	`0xfffffffc`	`0x0`
missing definiton	2	3	`NA`	`NA`	`NA`
CM_TIMERCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TIMERCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_TIMERCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TIMERCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TIMERCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_TIMERDIV

Address: `0x7e1010ec`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TIMERDIV_DIV	0	17	`0x0003ffff`	`0xfffc0000`	`0x0`

CM_UARTCTL

Address: `0x7e1010f0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_UARTCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_UARTCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_UARTCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_UARTCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_UARTCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_UARTCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_UARTDIV

Address: `0x7e1010f4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_UARTDIV_DIV	0	21	`0x003fffff`	`0xffc00000`	`0x0`

CM_VECCTL

Address: `0x7e1010f8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_VECCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_VECCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_VECCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_VECCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_VECCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_VECCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_VECDIV

Address: `0x7e1010fc`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_VECDIV_DIV	12	15	`0x0000f000`	`0xffff0fff`	`0x0`

CM_OSCCOUNT

Address: `0x7e101100`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_OSCCOUNT_NUM	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLA

Address: `0x7e101104`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLA_LOADDSI0	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_PLLA_HOLDDSI0	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_PLLA_LOADCCP2	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_PLLA_HOLDCCP2	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_PLLA_LOADCORE	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_PLLA_HOLDCORE	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_PLLA_LOADPER	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_PLLA_HOLDPER	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PLLA_ANARST	8	8	`0x00000100`	`0xfffffeff`	`0x1`
CM_PLLA_DIGRST	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLC

Address: `0x7e101108`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLC_LOADCORE0	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_PLLC_HOLDCORE0	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_PLLC_LOADCORE1	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_PLLC_HOLDCORE1	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_PLLC_LOADCORE2	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_PLLC_HOLDCORE2	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_PLLC_LOADPER	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_PLLC_HOLDPER	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PLLC_ANARST	8	8	`0x00000100`	`0xfffffeff`	`0x1`
CM_PLLC_DIGRST	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLD

Address: `0x7e10110c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLD_LOADDSI0	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_PLLD_HOLDDSI0	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_PLLD_LOADDSI1	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_PLLD_HOLDDSI1	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_PLLD_LOADCORE	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_PLLD_HOLDCORE	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_PLLD_LOADPER	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_PLLD_HOLDPER	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PLLD_ANARST	8	8	`0x00000100`	`0xfffffeff`	`0x1`
CM_PLLD_DIGRST	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PLLH

Address: `0x7e101110`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLH_LOADPIX	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_PLLH_LOADAUX	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_PLLH_LOADRCAL	2	2	`0x00000004`	`0xfffffffb`	`0x0`
missing definiton	3	7	`NA`	`NA`	`NA`
CM_PLLH_ANARST	8	8	`0x00000100`	`0xfffffeff`	`0x1`
CM_PLLH_DIGRST	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_LOCK

Address: `0x7e101114`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_LOCK_LOCKA	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_LOCK_LOCKB	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_LOCK_LOCKC	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_LOCK_LOCKD	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_LOCK_LOCKH	4	4	`0x00000010`	`0xffffffef`	`0x0`
missing definiton	5	7	`NA`	`NA`	`NA`
CM_LOCK_FLOCKA	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_LOCK_FLOCKB	9	9	`0x00000200`	`0xfffffdff`	`0x0`
CM_LOCK_FLOCKC	10	10	`0x00000400`	`0xfffffbff`	`0x0`
CM_LOCK_FLOCKD	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_LOCK_FLOCKH	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_EVENT

Address: `0x7e101118`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_EVENT_GAINA	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_EVENT_GAINB	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_EVENT_GAINC	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_EVENT_GAIND	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_EVENT_GAINH	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_EVENT_LOSSA	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_EVENT_LOSSB	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_EVENT_LOSSC	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_EVENT_LOSSD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_EVENT_LOSSH	9	9	`0x00000200`	`0xfffffdff`	`0x0`
CM_EVENT_FGAINA	10	10	`0x00000400`	`0xfffffbff`	`0x0`
CM_EVENT_FGAINB	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_EVENT_FGAINC	12	12	`0x00001000`	`0xffffefff`	`0x0`
CM_EVENT_FGAIND	13	13	`0x00002000`	`0xffffdfff`	`0x0`
CM_EVENT_FLOSSA	14	14	`0x00004000`	`0xffffbfff`	`0x0`
CM_EVENT_FLOSSB	15	15	`0x00008000`	`0xffff7fff`	`0x0`
CM_EVENT_FLOSSC	16	16	`0x00010000`	`0xfffeffff`	`0x0`
CM_EVENT_FLOSSD	17	17	`0x00020000`	`0xfffdffff`	`0x0`
CM_EVENT_BADPASS	18	18	`0x00040000`	`0xfffbffff`	`0x0`
CM_EVENT_WRFAIL	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
CM_EVENT_A2WDONE	20	20	`0x00100000`	`0xffefffff`	`0x0`
CM_EVENT_OCDONE	21	21	`0x00200000`	`0xffdfffff`	`0x0`
CM_EVENT_RESUS	22	22	`0x00400000`	`0xffbfffff`	`0x0`
CM_EVENT_BURSTDONE	23	23	`0x00800000`	`0xff7fffff`	`0x0`

CM_INTEN

Address: `0x7e10111c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_INTEN_GAINA	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_INTEN_GAINB	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_INTEN_GAINC	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_INTEN_GAIND	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_INTEN_GAINH	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_INTEN_LOSSA	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_INTEN_LOSSB	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_INTEN_LOSSC	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_INTEN_LOSSD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_INTEN_LOSSH	9	9	`0x00000200`	`0xfffffdff`	`0x0`
CM_INTEN_FGAINA	10	10	`0x00000400`	`0xfffffbff`	`0x0`
CM_INTEN_FGAINB	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_INTEN_FGAINC	12	12	`0x00001000`	`0xffffefff`	`0x0`
CM_INTEN_FGAIND	13	13	`0x00002000`	`0xffffdfff`	`0x0`
CM_INTEN_FLOSSA	14	14	`0x00004000`	`0xffffbfff`	`0x0`
CM_INTEN_FLOSSB	15	15	`0x00008000`	`0xffff7fff`	`0x0`
CM_INTEN_FLOSSC	16	16	`0x00010000`	`0xfffeffff`	`0x0`
CM_INTEN_FLOSSD	17	17	`0x00020000`	`0xfffdffff`	`0x0`
CM_INTEN_BADPASS	18	18	`0x00040000`	`0xfffbffff`	`0x0`
CM_INTEN_WRFAIL	19	19	`0x00080000`	`0xfff7ffff`	`0x0`
CM_INTEN_A2WDONE	20	20	`0x00100000`	`0xffefffff`	`0x0`
CM_INTEN_OCDONE	21	21	`0x00200000`	`0xffdfffff`	`0x0`
CM_INTEN_RESUS	22	22	`0x00400000`	`0xffbfffff`	`0x0`
CM_INTEN_BURSTDONE	23	23	`0x00800000`	`0xff7fffff`	`0x0`

CM_DSI0HSCK

Address: `0x7e101120`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DSI0HSCK_SELPLLD	0	0	`0x00000001`	`0xfffffffe`	`0x0`

CM_CKSM

Address: `0x7e101124`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_CKSM_STATE	0	7	`0x000000ff`	`0xffffff00`	`0x0`
CM_CKSM_FRCE	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`
CM_CKSM_CFG	16	17	`0x00030000`	`0xfffcffff`	`0x0`
CM_CKSM_OSC	18	19	`0x000c0000`	`0xfff3ffff`	`0x0`
CM_CKSM_AUTO	20	20	`0x00100000`	`0xffefffff`	`0x0`
CM_CKSM_STEP	21	21	`0x00200000`	`0xffdfffff`	`0x0`

CM_OSCFREQI

Address: `0x7e101128`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_OSCFREQI_INT	0	7	`0x000000ff`	`0xffffff00`	`0x0`

CM_OSCFREQF

Address: `0x7e10112c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_OSCFREQF_FRAC	0	19	`0x000fffff`	`0xfff00000`	`0x0`

CM_PLLTCTL

Address: `0x7e101130`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLTCTL_SRC	0	2	`0x00000007`	`0xfffffff8`	`0x0`
missing definiton	3	4	`NA`	`NA`	`NA`
CM_PLLTCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_PLLTCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`

CM_PLLTCNT0

Address: `0x7e101134`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLTCNT0_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT1

Address: `0x7e101138`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLTCNT1_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT2

Address: `0x7e10113c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLTCNT2_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_PLLTCNT3

Address: `0x7e101140`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLTCNT3_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_TDCLKEN

Address: `0x7e101144`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_TDCLKEN_PLLABYP	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_TDCLKEN_PLLBBYP	1	1	`0x00000002`	`0xfffffffd`	`0x0`
CM_TDCLKEN_PLLCBYP	2	2	`0x00000004`	`0xfffffffb`	`0x0`
CM_TDCLKEN_PLLDBYP	3	3	`0x00000008`	`0xfffffff7`	`0x0`
CM_TDCLKEN_PLLADIV2	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_TDCLKEN_PLLBDIV2	5	5	`0x00000020`	`0xffffffdf`	`0x0`
CM_TDCLKEN_PLLCDIV2	6	6	`0x00000040`	`0xffffffbf`	`0x0`
CM_TDCLKEN_PLLDDIV2	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_TDCLKEN_HDMIBYP	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_TDCLKEN_MPHIWDFT	9	9	`0x00000200`	`0xfffffdff`	`0x0`
CM_TDCLKEN_MPHIRDFT	10	10	`0x00000400`	`0xfffffbff`	`0x0`
CM_TDCLKEN_USBDFT	11	11	`0x00000800`	`0xfffff7ff`	`0x0`
CM_TDCLKEN_SLIMDFT	12	12	`0x00001000`	`0xffffefff`	`0x0`
CM_TDCLKEN_IMAGETD	13	13	`0x00002000`	`0xffffdfff`	`0x0`

CM_BURSTCTL

Address: `0x7e101148`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_BURSTCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_BURSTCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_BURSTCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`

CM_BURSTCNT

Address: `0x7e10114c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_BURSTCNT_CNT	0	23	`0x00ffffff`	`0xff000000`	`0x0`

CM_DSI1ECTL

Address: `0x7e101158`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DSI1ECTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DSI1ECTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_DSI1ECTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_DSI1ECTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DSI1ECTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DSI1ECTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI1EDIV

Address: `0x7e10115c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_DSI1EDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

CM_DSI1PCTL

Address: `0x7e101160`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DSI1PCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DSI1PCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
missing definiton	5	6	`NA`	`NA`	`NA`
CM_DSI1PCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DSI1PCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DSI1PCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DSI1PDIV

Address: `0x7e101164`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_DSI1PDIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_DFTCTL

Address: `0x7e101168`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_DFTCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_DFTCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_DFTCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_DFTCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_DFTCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_DFTCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_DFTDIV

Address: `0x7e10116c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_DFTDIV_DIV	12	16	`0x0001f000`	`0xfffe0fff`	`0x0`

CM_PLLB

Address: `0x7e101170`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PLLB_LOADARM	0	0	`0x00000001`	`0xfffffffe`	`0x0`
CM_PLLB_HOLDARM	1	1	`0x00000002`	`0xfffffffd`	`0x0`
missing definiton	2	7	`NA`	`NA`	`NA`
CM_PLLB_ANARST	8	8	`0x00000100`	`0xfffffeff`	`0x1`
CM_PLLB_DIGRST	9	9	`0x00000200`	`0xfffffdff`	`0x1`

CM_PULSECTL

Address: `0x7e101190`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_PULSECTL_SRC	0	1	`0x00000003`	`0xfffffffc`	`0x1`
missing definiton	2	3	`NA`	`NA`	`NA`
CM_PULSECTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x1`
CM_PULSECTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_PULSECTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_PULSECTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_PULSECTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_PULSEDIV

Address: `0x7e101194`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_PULSEDIV_DIV	12	23	`0x00fff000`	`0xff000fff`	`0x1b`

CM_SDCCTL

Address: `0x7e1011a8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_SDCCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_SDCCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_SDCCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_SDCCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_SDCCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_SDCCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
CM_SDCCTL_CTRL	12	15	`0x0000f000`	`0xffff0fff`	`0x4`
CM_SDCCTL_ACCPT	16	16	`0x00010000`	`0xfffeffff`	`0x0`
CM_SDCCTL_UPDATE	17	17	`0x00020000`	`0xfffdffff`	`0x0`

CM_SDCDIV

Address: `0x7e1011ac`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_SDCDIV_DIV	12	17	`0x0003f000`	`0xfffc0fff`	`0x0`

CM_ARMCTL

Address: `0x7e1011b0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_ARMCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x4`
CM_ARMCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_ARMCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_ARMCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_ARMCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_ARMCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`
missing definiton	10	11	`NA`	`NA`	`NA`
CM_ARMCTL_AXIHALF	12	12	`0x00001000`	`0xffffefff`	`0x0`

CM_ARMDIV

Address: `0x7e1011b4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_ARMDIV_DIV	12	12	`0x00001000`	`0xffffefff`	`0x1`

CM_AVEOCTL

Address: `0x7e1011b8`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_AVEOCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_AVEOCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_AVEOCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_AVEOCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_AVEOCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_AVEOCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_AVEODIV

Address: `0x7e1011bc`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	11	`NA`	`NA`	`NA`
CM_AVEODIV_DIV	12	15	`0x0000f000`	`0xffff0fff`	`0x0`

CM_EMMCCTL

Address: `0x7e1011c0`

Field Name	Start Bit	End Bit	Set	Clear	Reset
CM_EMMCCTL_SRC	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
CM_EMMCCTL_ENAB	4	4	`0x00000010`	`0xffffffef`	`0x0`
CM_EMMCCTL_KILL	5	5	`0x00000020`	`0xffffffdf`	`0x0`
missing definiton	6	6	`NA`	`NA`	`NA`
CM_EMMCCTL_BUSY	7	7	`0x00000080`	`0xffffff7f`	`0x0`
CM_EMMCCTL_BUSYD	8	8	`0x00000100`	`0xfffffeff`	`0x0`
CM_EMMCCTL_FRAC	9	9	`0x00000200`	`0xfffffdff`	`0x0`

CM_EMMCDIV

Address: `0x7e1011c4`

Field Name	Start Bit	End Bit	Set	Clear	Reset
missing definiton	0	3	`NA`	`NA`	`NA`
CM_EMMCDIV_DIV	4	15	`0x0000fff0`	`0xffff000f`	`0x0`

<< RPi Registers Index

Register Region: CM (0x7e101000)

Info

Registers

Register info

Address: 0x7e101000

Address: 0x7e101004

Address: 0x7e101008

Address: 0x7e10100c

Address: 0x7e101010

Address: 0x7e101014

Address: 0x7e101018

Address: 0x7e10101c

Address: 0x7e101020

Address: 0x7e101024

Address: 0x7e101028

Address: 0x7e10102c

Address: 0x7e101030

Address: 0x7e101034

Address: 0x7e101038

Address: 0x7e10103c

Address: 0x7e101040

Address: 0x7e101044

Address: 0x7e101048

Address: 0x7e10104c

Address: 0x7e101050

Address: 0x7e101054

Address: 0x7e101058

Address: 0x7e10105c

Address: 0x7e101060

Address: 0x7e101064

Address: 0x7e101068

Address: 0x7e10106c

Address: 0x7e101070

Address: 0x7e101074

Address: 0x7e101078

Address: 0x7e10107c

Address: 0x7e101080

Address: 0x7e101084

Address: 0x7e101088

Address: 0x7e10108c

Address: 0x7e101090

Address: 0x7e101094

Address: 0x7e101098

Address: 0x7e10109c

Address: 0x7e1010a0

Address: 0x7e1010a4

Address: 0x7e1010a8

Address: 0x7e1010ac

Address: 0x7e1010b0

Address: 0x7e1010b4

Address: 0x7e1010c0

Address: 0x7e1010c4

Address: 0x7e1010c8

Address: 0x7e1010cc

Address: 0x7e1010d0

Address: 0x7e1010d4

Address: 0x7e1010d8

Address: 0x7e1010dc

Address: 0x7e1010e0

Address: 0x7e1010e4

Address: 0x7e1010e8

Address: 0x7e1010ec

Address: 0x7e1010f0

Address: 0x7e1010f4

Address: 0x7e1010f8

Address: 0x7e1010fc

Address: 0x7e101100

Address: 0x7e101104

Address: 0x7e101108

Address: 0x7e10110c

Address: 0x7e101110

Address: 0x7e101114

Address: 0x7e101118

Address: 0x7e10111c

Address: 0x7e101120

Address: 0x7e101124

Address: 0x7e101128

Register Region: CM (`0x7e101000`)

Address: `0x7e101000`

Address: `0x7e101004`

Address: `0x7e101008`

Address: `0x7e10100c`

Address: `0x7e101010`

Address: `0x7e101014`

Address: `0x7e101018`

Address: `0x7e10101c`

Address: `0x7e101020`

Address: `0x7e101024`

Address: `0x7e101028`

Address: `0x7e10102c`

Address: `0x7e101030`

Address: `0x7e101034`

Address: `0x7e101038`

Address: `0x7e10103c`

Address: `0x7e101040`

Address: `0x7e101044`

Address: `0x7e101048`

Address: `0x7e10104c`

Address: `0x7e101050`

Address: `0x7e101054`

Address: `0x7e101058`

Address: `0x7e10105c`

Address: `0x7e101060`

Address: `0x7e101064`

Address: `0x7e101068`

Address: `0x7e10106c`

Address: `0x7e101070`

Address: `0x7e101074`

Address: `0x7e101078`

Address: `0x7e10107c`

Address: `0x7e101080`

Address: `0x7e101084`

Address: `0x7e101088`

Address: `0x7e10108c`

Address: `0x7e101090`

Address: `0x7e101094`

Address: `0x7e101098`

Address: `0x7e10109c`

Address: `0x7e1010a0`

Address: `0x7e1010a4`

Address: `0x7e1010a8`

Address: `0x7e1010ac`

Address: `0x7e1010b0`

Address: `0x7e1010b4`

Address: `0x7e1010c0`

Address: `0x7e1010c4`

Address: `0x7e1010c8`

Address: `0x7e1010cc`

Address: `0x7e1010d0`

Address: `0x7e1010d4`

Address: `0x7e1010d8`

Address: `0x7e1010dc`

Address: `0x7e1010e0`

Address: `0x7e1010e4`

Address: `0x7e1010e8`

Address: `0x7e1010ec`

Address: `0x7e1010f0`

Address: `0x7e1010f4`

Address: `0x7e1010f8`

Address: `0x7e1010fc`

Address: `0x7e101100`

Address: `0x7e101104`

Address: `0x7e101108`

Address: `0x7e10110c`

Address: `0x7e101110`

Address: `0x7e101114`

Address: `0x7e101118`

Address: `0x7e10111c`

Address: `0x7e101120`

Address: `0x7e101124`

Address: `0x7e101128`