Register Region: SYSAC (`0x7e009000`)

Info

Name	Value
base	`0x7e009000`
id	`0x4152424d`

Registers

Register Name	Address	Type	Width	Mask	Reset
SYSAC_HOST_PRIORITY	`0x7e009000`	RW	4	`0x0000000f`	`0000000000`
SYSAC_DBG_PRIORITY	`0x7e009004`	RW	4	`0x0000000f`	`0000000000`
SYSAC_HVSM_PRIORITY	`0x7e009008`	RW	8	`0x000000ff`	`0000000000`
SYSAC_V3D_PRIORITY	`0x7e00900c`	RW	4	`0x0000000f`	`0000000000`
SYSAC_H264_PRIORITY	`0x7e009010`	RW	4	`0x0000000f`	`0000000000`
SYSAC_JPEG_PRIORITY	`0x7e009014`	RW	8	`0x000000ff`	`0000000000`
SYSAC_TRANS_PRIORITY	`0x7e009018`	RW	8	`0x000000ff`	`0000000000`
SYSAC_ISP_PRIORITY	`0x7e00901c`	RW	4	`0x0000000f`	`0000000000`
SYSAC_USB_PRIORITY	`0x7e009020`	RW	4	`0x0000000f`	`0000000000`
SYSAC_L2_ARBITER_CONTROL	`0x7e009040`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_UC_ARBITER_CONTROL	`0x7e009044`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_SRC_ARBITER_CONTROL	`0x7e009048`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_PERI_ARBITER_CONTROL	`0x7e00904c`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_DMA_ARBITER_CONTROL_UC	`0x7e009050`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_DMA_ARBITER_CONTROL_L2	`0x7e009054`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_DMA_ARBITER_CONTROL_PER	`0x7e009058`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_DMA_ARBITER_CONTROL_LITE	`0x7e00905c`	RW	16	`0x0000ffff`	`0000000000`
SYSAC_DUMMY_STATUS	`0x7e009060`	RW	1	`0x00000001`	`0000000000`
SYSAC_DMA_DREQ_CONTROL	`0x7e009064`	RW	4	`0x0000000f`	`0000000000`
SYSAC_V3D_LIMITER	`0x7e009068`	RW	12	`0x00000fff`	`0000000000`

Unsupported Defines

Define	Value
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0

Register info

SYSAC_HOST_PRIORITY

Address: `0x7e009000`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_HOST_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_DBG_PRIORITY

Address: `0x7e009004`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DBG_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_HVSM_PRIORITY

Address: `0x7e009008`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_HVSM_PRIORITY_N_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
SYSAC_HVSM_PRIORITY_P_PRIORITY	4	7	`0x000000f0`	`0xffffff0f`	`0x0`

SYSAC_V3D_PRIORITY

Address: `0x7e00900c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_V3D_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_H264_PRIORITY

Address: `0x7e009010`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_H264_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_JPEG_PRIORITY

Address: `0x7e009014`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_JPEG_PRIORITY_N_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
SYSAC_JPEG_PRIORITY_P_PRIORITY	4	7	`0x000000f0`	`0xffffff0f`	`0x0`

SYSAC_TRANS_PRIORITY

Address: `0x7e009018`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_TRANS_PRIORITY_N_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`
SYSAC_TRANS_PRIORITY_P_PRIORITY	4	7	`0x000000f0`	`0xffffff0f`	`0x0`

SYSAC_ISP_PRIORITY

Address: `0x7e00901c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_ISP_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_USB_PRIORITY

Address: `0x7e009020`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_USB_PRIORITY_PRIORITY	0	3	`0x0000000f`	`0xfffffff0`	`0x0`

SYSAC_L2_ARBITER_CONTROL

Address: `0x7e009040`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_L2_ARBITER_CONTROL_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_L2_ARBITER_CONTROL_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_L2_ARBITER_CONTROL_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_L2_ARBITER_CONTROL_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_UC_ARBITER_CONTROL

Address: `0x7e009044`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_UC_ARBITER_CONTROL_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_UC_ARBITER_CONTROL_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_UC_ARBITER_CONTROL_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_UC_ARBITER_CONTROL_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_SRC_ARBITER_CONTROL

Address: `0x7e009048`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_SRC_ARBITER_CONTROL_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_SRC_ARBITER_CONTROL_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_SRC_ARBITER_CONTROL_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_SRC_ARBITER_CONTROL_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_PERI_ARBITER_CONTROL

Address: `0x7e00904c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_PERI_ARBITER_CONTROL_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_PERI_ARBITER_CONTROL_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_PERI_ARBITER_CONTROL_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_PERI_ARBITER_CONTROL_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_DMA_ARBITER_CONTROL_UC

Address: `0x7e009050`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_UC_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_DMA_ARBITER_CONTROL_L2

Address: `0x7e009054`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_L2_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`

SYSAC_DMA_ARBITER_CONTROL_PER

Address: `0x7e009058`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_PER_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_DMA_ARBITER_CONTROL_LITE

Address: `0x7e00905c`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT	0	1	`0x00000003`	`0xfffffffc`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY	2	3	`0x0000000c`	`0xfffffff3`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD	4	5	`0x00000030`	`0xffffffcf`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM	6	7	`0x000000c0`	`0xffffff3f`	`0x0`
SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT	8	15	`0x0000ff00`	`0xffff00ff`	`0x0`

SYSAC_DUMMY_STATUS

Address: `0x7e009060`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DUMMY_STATUS_IDLE	0	0	`0x00000001`	`0xfffffffe`	`0x0`

SYSAC_DMA_DREQ_CONTROL

Address: `0x7e009064`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE	0	2	`0x00000007`	`0xfffffff8`	`0x0`
SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR	3	3	`0x00000008`	`0xfffffff7`	`0x0`

SYSAC_V3D_LIMITER

Address: `0x7e009068`

Field Name	Start Bit	End Bit	Set	Clear	Reset
SYSAC_V3D_LIMITER_HOLDOFF	0	0	`0x00000001`	`0xfffffffe`	`0x0`
SYSAC_V3D_LIMITER_ENABLE	0	0	`0x00000001`	`0xfffffffe`	`0x0`
SYSAC_V3D_LIMITER_INCREMENT	0	0	`0x00000001`	`0xfffffffe`	`0x0`
missing definiton	1	-1	`NA`	`NA`	`NA`
SYSAC_V3D_LIMITER_SPARE	1	3	`0x0000000e`	`0xfffffff1`	`0x0`
SYSAC_V3D_LIMITER_MAX_PRIORITY	3	7	`0x000000f8`	`0xffffff07`	`0x0`
missing definiton	4	2	`NA`	`NA`	`NA`

<< RPi Registers Index

Register Region: SYSAC (0x7e009000)

Info

Registers

Unsupported Defines

Register info

Address: 0x7e009000

Address: 0x7e009004

Address: 0x7e009008

Address: 0x7e00900c

Address: 0x7e009010

Address: 0x7e009014

Address: 0x7e009018

Address: 0x7e00901c

Address: 0x7e009020

Address: 0x7e009040

Address: 0x7e009044

Address: 0x7e009048

Address: 0x7e00904c

Address: 0x7e009050

Address: 0x7e009054

Address: 0x7e009058

Address: 0x7e00905c

Address: 0x7e009060

Address: 0x7e009064

Address: 0x7e009068

Register Region: SYSAC (`0x7e009000`)

Address: `0x7e009000`

Address: `0x7e009004`

Address: `0x7e009008`

Address: `0x7e00900c`

Address: `0x7e009010`

Address: `0x7e009014`

Address: `0x7e009018`

Address: `0x7e00901c`

Address: `0x7e009020`

Address: `0x7e009040`

Address: `0x7e009044`

Address: `0x7e009048`

Address: `0x7e00904c`

Address: `0x7e009050`

Address: `0x7e009054`

Address: `0x7e009058`

Address: `0x7e00905c`

Address: `0x7e009060`

Address: `0x7e009064`

Address: `0x7e009068`