| Define | Value |
|---|
| ACISASR_REG | 0x1c004814:RW |
| ACISCA_REG | 0x1c004808:RW |
| ACISCD_REG | 0x1c00480c:RW |
| ACISCS_REG | 0x1c004800:RW |
| ACISFIFO_REG | 0x1c004804:RW |
| ACISMODE_REG | 0x1c004810:RW |
| ACIS_BASE_ADDRESS | 0x1C004800 |
| ACIS_DMA | 0 |
| AC_HUFFTABLE_OFFSET(t) | MACRO |
| AC_MAXCTABLE_OFFSET(t) | MACRO |
| AC_OSETTABLE_OFFSET(t) | MACRO |
| ADCCS_REG | 0x1c00e000:RW |
| ADCR0_REG | 0x1c00e004:RW |
| ADCR1_REG | 0x1c00e008:RW |
| ADC_BASE_ADDRESS | 0x1C00E000 |
| ADC_DMA | 0xf0000 |
| ADDRESS_EXTERNAL(p) | MACRO |
| AJBCONF_REG | 0x7e2000c0:RW |
| AJBTDI_REG | 0x7e2000c8:RW |
| AJBTDO_REG | 0x7e2000cc:RW |
| AJBTMS_REG | 0x7e2000c4:RW |
| AJB_BITS0 | 0x000000 |
| AJB_BITS12 | 0x00000C |
| AJB_BITS16 | 0x000010 |
| AJB_BITS20 | 0x000014 |
| AJB_BITS24 | 0x000018 |
| AJB_BITS28 | 0x00001C |
| AJB_BITS32 | 0x000020 |
| AJB_BITS34 | 0x000022 |
| AJB_BITS4 | 0x000004 |
| AJB_BITS8 | 0x000008 |
| AJB_BUSY | 0x80000000 |
| AJB_CLKSHFT | 16 |
| AJB_D0_FALL | 0x000000 |
| AJB_D0_RISE | 0x000100 |
| AJB_D1_FALL | 0x000000 |
| AJB_D1_RISE | 0x000200 |
| AJB_ENABLE | 0x000800 |
| AJB_HOLD0 | 0x000000 |
| AJB_HOLD1 | 0x001000 |
| AJB_HOLD2 | 0x002000 |
| AJB_HOLD3 | 0x003000 |
| AJB_INV_CLK | 0x000080 |
| AJB_IN_FALL | 0x000000 |
| AJB_IN_RISE | 0x000400 |
| AJB_OUT_LS | 0x000000 |
| AJB_OUT_MS | 0x000040 |
| AJB_RESETN | 0x004000 |
| ALIAS_ANY_L1_NONALLOCATING(x) | MACRO |
| ALIAS_ANY_NONALLOCATING(x) | MACRO |
| ALIAS_ANY_NONALLOCATING_READ(x) | MACRO |
| ALIAS_COHERENT(x) | MACRO |
| ALIAS_DIRECT(x) | MACRO |
| ALIAS_L1L2_NONALLOCATING(x) | MACRO |
| ALIAS_L1L2_NONALLOCATING_READ(x) | MACRO |
| ALIAS_L1_NONALLOCATING(x) | MACRO |
| ALIAS_NORMAL(x) | MACRO |
| ALIAS_STREAMING(x) | MACRO |
| AM_DB_MEMPRI_REG | 0x1800d014:RW |
| AM_DB_PERPRI_REG | 0x1800d018:RW |
| AM_HO_MEMPRI_REG | 0x1800d00c:RW |
| AM_HO_PERPRI_REG | 0x1800d010:RW |
| AM_HVSM_PRI_REG | 0x1800d01c:RW |
| AM_VP_L2_PRI_REG | 0x1800d000:RW |
| AM_VP_PERPRI_REG | 0x1800d008:RW |
| AM_VP_UC_PRI_REG | 0x1800d004:RW |
| BIT_STREAM_DMA | 0 |
| BOOTROM_BASE_ADDRESS | 0x10000000 |
| BOOTROM_BRCTL_REG | 0x1000c000:RW |
| BOOTROM_RAM_LENGTH | ( 1024 * 2 ) |
| BOOTROM_RAM_START | 0x10008000 |
| BOOTROM_ROM_LENGTH | ( 1024 * 32 ) |
| BOOTROM_ROM_START | 0x10000000 |
| CAM_DMA | 0 |
| CCP2RBC0_REG | CCP2_BASE_ADDRESS + 0x118:RO |
| CCP2RBC1_REG | CCP2_BASE_ADDRESS + 0x218:RO |
| CCP2RC0_REG | CCP2_BASE_ADDRESS + 0x100:RW |
| CCP2RC1_REG | CCP2_BASE_ADDRESS + 0x200:RW |
| CCP2RC_REG | CCP2_BASE_ADDRESS + 0x00:RW |
| CCP2RDEA0_REG | CCP2_BASE_ADDRESS + 0x124:RW |
| CCP2RDEA1_REG | CCP2_BASE_ADDRESS + 0x224:RW |
| CCP2RDR1_REG | CCP2_BASE_ADDRESS + 0x80:RO |
| CCP2RDR2_REG | CCP2_BASE_ADDRESS + 0x84:RO |
| CCP2RDR3_REG | CCP2_BASE_ADDRESS + 0x88:RO |
| CCP2RDS0_REG | CCP2_BASE_ADDRESS + 0x128:RW |
| CCP2RDS1_REG | CCP2_BASE_ADDRESS + 0x228:RW |
| CCP2RDSA0_REG | CCP2_BASE_ADDRESS + 0x120:RW |
| CCP2RDSA1_REG | CCP2_BASE_ADDRESS + 0x220:RW |
| CCP2REA0_REG | CCP2_BASE_ADDRESS + 0x110:RW |
| CCP2REA1_REG | CCP2_BASE_ADDRESS + 0x210:RW |
| CCP2RLS0_REG | CCP2_BASE_ADDRESS + 0x11C:RW |
| CCP2RLS1_REG | CCP2_BASE_ADDRESS + 0x21C:RW |
| CCP2RPC0_REG | CCP2_BASE_ADDRESS + 0x104:RW |
| CCP2RPC1_REG | CCP2_BASE_ADDRESS + 0x204:RW |
| CCP2RS0_REG | CCP2_BASE_ADDRESS + 0x108:RW |
| CCP2RS1_REG | CCP2_BASE_ADDRESS + 0x208:RW |
| CCP2RSA0_REG | CCP2_BASE_ADDRESS + 0x10C:RW |
| CCP2RSA1_REG | CCP2_BASE_ADDRESS + 0x20C:RW |
| CCP2RS_REG | CCP2_BASE_ADDRESS + 0x04:RW |
| CCP2RWP0_REG | CCP2_BASE_ADDRESS + 0x114:RO |
| CCP2RWP1_REG | CCP2_BASE_ADDRESS + 0x214:RO |
| CCP2TAC_REG | 0x7e001008:RW |
| CCP2TBA_REG | 0x7e00101c:RW |
| CCP2TC_REG | 0x7e001000:RW |
| CCP2TDL_REG | 0x7e001020:RW |
| CCP2TD_REG | 0x7e001024:RW |
| CCP2TIC_REG | 0x7e001014:RW |
| CCP2TPC_REG | 0x7e00100c:RW |
| CCP2TSC_REG | 0x7e001010:RW |
| CCP2TSPARE_REG | 0x7e001028:RW |
| CCP2TS_REG | 0x7e001004:RW |
| CCP2TTC_REG | 0x7e001018:RW |
| CDPC_REG | 0x1c00e000:RW |
| CDP_BASE | 0x1C00E000 |
| CDP_DEBUG0_REG | 0x1c00e00c:RW |
| CDP_DEBUG1_REG | 0x1c00e010:RW |
| CDP_PHYC_REG | 0x1c00e004:RW |
| CDP_PHYTSTDAT_REG | 0x1c00e008:RW |
| CGMSAE_BOT_CONTROL_REG | 0x7e806048:RW |
| CGMSAE_BOT_DATA_REG | 0x7e806058:RW |
| CGMSAE_BOT_FORMAT_REG | 0x7e806050:RW |
| CGMSAE_RESET_REG | 0x7e806040:RW |
| CGMSAE_REVID_REG | 0x7e80605c:RW |
| CGMSAE_TOP_CONTROL_REG | 0x7e806044:RW |
| CGMSAE_TOP_DATA_REG | 0x7e806054:RW |
| CGMSAE_TOP_FORMAT_REG | 0x7e80604c:RW |
| CLR_GPIO(g) | MACRO |
| CMACIS_REG | 0x7C:RW |
| CMCAM_REG | 0x7C:RW |
| CMCORE_REG | 0x7C:RW |
| CMGEN_REG | 0x7C:RW |
| CMLCD_REG | 0x7C:RW |
| CMMSP_REG | 0x7C:RW |
| CMNVT_REG | 0x7C:RW |
| CMPCM_REG | 0x7C:RW |
| CMPLL1_REG | 0x7C:RW |
| CMPLL2_REG | 0x7C:RW |
| CMPLL3_REG | 0x7C:RW |
| CMPLLC_REG | 0x7C:RW |
| CMPRE1_REG | 0x7C:RW |
| CMPRE2_REG | 0x7C:RW |
| CMPRE3_REG | 0x7C:RW |
| CMPREC_REG | 0x7C:RW |
| CMTIMERF_REG | 0x7C:RW |
| CMTIMER_REG | 0x7C:RW |
| CMUARTF_REG | 0x7C:RW |
| CMUART_REG | 0x7C:RW |
| CMUSB_REG | 0x7C:RW |
| CRYPTO_IP_DMA | 0x130000 |
| CRYPTO_ISR_REG | 0x7e00200c:RO |
| CRYPTO_ISR_RNG_INT | 0x0100000 |
| CRYPTO_OP_DMA | 0x140000 |
| CSI2DBGDPHY_REG | CSI2_BASE_ADDRESS + 0x80:RW |
| CSI2DBGMISC_REG | CSI2_BASE_ADDRESS + 0x84:RW |
| CSI2LPRX0_REG | CSI2_BASE_ADDRESS + 0x20:RW |
| CSI2LPRX1_REG | CSI2_BASE_ADDRESS + 0x24:RW |
| CSI2LPRX2_REG | CSI2_BASE_ADDRESS + 0x28:RW |
| CSI2LPRX3_REG | CSI2_BASE_ADDRESS + 0x2C:RW |
| CSI2LPRXC_REG | CSI2_BASE_ADDRESS + 0x30:RW |
| CSI2RDR3_REG | CSI2_BASE_ADDRESS + 0x94:RW |
| CSI2TRIG_REG | CSI2_BASE_ADDRESS + 0x40:RW |
| CSI2_DTOV0_REG | CSI2_BASE_ADDRESS + 0x12C:RW |
| CSI2_DTOV1_REG | CSI2_BASE_ADDRESS + 0x22C:RW |
| CSI2_DTOV_x(x) | MACRO |
| CSI2_RBC0_REG | CSI2_BASE_ADDRESS + 0x118:RW |
| CSI2_RBC1_REG | CSI2_BASE_ADDRESS + 0x218:RW |
| CSI2_RBC_x(x) | MACRO |
| CSI2_RC0_REG | CSI2_BASE_ADDRESS + 0x100:RW |
| CSI2_RC1_REG | CSI2_BASE_ADDRESS + 0x200:RW |
| CSI2_RC_REG | CSI2_BASE_ADDRESS + 0x00:RW |
| CSI2_RC_x(x) | MACRO |
| CSI2_RDEA0_REG | CSI2_BASE_ADDRESS + 0x124:RW |
| CSI2_RDEA1_REG | CSI2_BASE_ADDRESS + 0x224:RW |
| CSI2_RDEA_x(x) | MACRO |
| CSI2_RDLS_REG | CSI2_BASE_ADDRESS + 0x08:RW |
| CSI2_RDS0_REG | CSI2_BASE_ADDRESS + 0x128:RW |
| CSI2_RDS1_REG | CSI2_BASE_ADDRESS + 0x228:RW |
| CSI2_RDSA0_REG | CSI2_BASE_ADDRESS + 0x120:RW |
| CSI2_RDSA1_REG | CSI2_BASE_ADDRESS + 0x220:RW |
| CSI2_RDSA_x(x) | MACRO |
| CSI2_RDS_x(x) | MACRO |
| CSI2_REA0_REG | CSI2_BASE_ADDRESS + 0x110:RW |
| CSI2_REA1_REG | CSI2_BASE_ADDRESS + 0x210:RW |
| CSI2_REA_x(x) | MACRO |
| CSI2_RGSP_REG | CSI2_BASE_ADDRESS + 0x0C:RW |
| CSI2_RLS0_REG | CSI2_BASE_ADDRESS + 0x11C:RW |
| CSI2_RLS1_REG | CSI2_BASE_ADDRESS + 0x21C:RW |
| CSI2_RLS_x(x) | MACRO |
| CSI2_RPC0_REG | CSI2_BASE_ADDRESS + 0x104:RW |
| CSI2_RPC1_REG | CSI2_BASE_ADDRESS + 0x204:RW |
| CSI2_RPC_x(x) | MACRO |
| CSI2_RS0_REG | CSI2_BASE_ADDRESS + 0x108:RW |
| CSI2_RS1_REG | CSI2_BASE_ADDRESS + 0x208:RW |
| CSI2_RSA0_REG | CSI2_BASE_ADDRESS + 0x10C:RW |
| CSI2_RSA1_REG | CSI2_BASE_ADDRESS + 0x20C:RW |
| CSI2_RSA_x(x) | MACRO |
| CSI2_RS_REG | CSI2_BASE_ADDRESS + 0x04:RW |
| CSI2_RS_x(x) | MACRO |
| CSI2_RWP0_REG | CSI2_BASE_ADDRESS + 0x114:RW |
| CSI2_RWP1_REG | CSI2_BASE_ADDRESS + 0x214:RW |
| CSI2_RWP_x(x) | MACRO |
| CSI2_SRST_REG | CSI2_BASE_ADDRESS + 0x90:RW |
| CSI2_THSCKTO_REG | CSI2_BASE_ADDRESS + 0x1C:RW |
| CSI2_THSSET_REG | CSI2_BASE_ADDRESS + 0x18:RW |
| CSI2_THSSTO_REG | CSI2_BASE_ADDRESS + 0x14:RW |
| CSI2_TREN_REG | CSI2_BASE_ADDRESS + 0x10:RW |
| D1CACHE_BASE_REG | 0xffffffff:RW |
| DC0CS_REG | 0x7ee02100:RW |
| DC0END_REG | 0x7ee02108:RW |
| DC0START_REG | 0x7ee02104:RW |
| DC1CS_REG | 0xffffffff:RW |
| DC1END_REG | 0xffffffff:RW |
| DC1START_REG | 0xffffffff:RW |
| DC_HUFFTABLE_OFFSET(t) | MACRO |
| DC_MAXCTABLE_OFFSET(t) | MACRO |
| DC_OSETTABLE_OFFSET(t) | MACRO |
| DISPC_BASE_ADDRESS | 0x1C009000 |
| DISP_DMA | 0 |
| DSI2_DMA | 0x100000 |
| DUMMYREG_REG | 0x7C:RW |
| GPAFEN0_REG | 0x7e200088:RW |
| GPAFEN1_REG | 0x7e20008c:RW |
| GPAFEN2_REG | 0x7e200090:RW |
| GPAREN0_REG | 0x7e20007c:RW |
| GPAREN1_REG | 0x7e200080:RW |
| GPAREN2_REG | 0x7e200084:RW |
| GPCLR0_REG | 0x7e200028:RW |
| GPCLR1_REG | 0x7e20002c:RW |
| GPCLR2_REG | 0x7e200030:RW |
| GPEDS0_REG | 0x7e200040:RW |
| GPEDS1_REG | 0x7e200044:RW |
| GPEDS2_REG | 0x7e200048:RW |
| GPFEN0_REG | 0x7e200058:RW |
| GPFEN1_REG | 0x7e20005c:RW |
| GPFEN2_REG | 0x7e200060:RW |
| GPFSEL0_REG | 0x7e200000:RW |
| GPFSEL1_REG | 0x7e200004:RW |
| GPFSEL2_REG | 0x7e200008:RW |
| GPFSEL3_REG | 0x7e20000c:RW |
| GPFSEL4_REG | 0x7e200010:RW |
| GPFSEL5_REG | 0x7e200014:RW |
| GPFSEL6_REG | 0x7e200018:RW |
| GPHEN0_REG | 0x7e200064:RW |
| GPHEN1_REG | 0x7e200068:RW |
| GPHEN2_REG | 0x7e20006c:RW |
| GPIO_MAX_PINS | 54 |
| GPLEN0_REG | 0x7e200070:RW |
| GPLEN1_REG | 0x7e200074:RW |
| GPLEN2_REG | 0x7e200078:RW |
| GPLEV0_REG | 0x7e200034:RW |
| GPLEV1_REG | 0x7e200038:RW |
| GPLEV2_REG | 0x7e20003c:RW |
| GPPUDCLK0_REG | 0x7e200098:RW |
| GPPUDCLK1_REG | 0x7e20009c:RW |
| GPPUDCLK2_REG | 0x7e2000a0:RW |
| GPPUD_REG | 0x7e200094:RW |
| GPREN0_REG | 0x7e20004c:RW |
| GPREN1_REG | 0x7e200050:RW |
| GPREN2_REG | 0x7e200054:RW |
| GPSET0_REG | 0x7e20001c:RW |
| GPSET1_REG | 0x7e200020:RW |
| GPSET2_REG | 0x7e200024:RW |
| GRDAADR0_REG | 0x1a005a40:RW |
| GRDAADR1_REG | 0x1a005a44:RW |
| GRDAADR2_REG | 0x1a005a48:RW |
| GRDAADR3_REG | 0x1a005a4c:RW |
| GRDAADR4_REG | 0x1a005a50:RW |
| GRDAADR5_REG | 0x1a005a54:RW |
| GRDAADR6_REG | 0x1a005a58:RW |
| GRDAADR7_REG | 0x1a005a5c:RW |
| GRDACFG0_REG | 0x1a005a20:RW |
| GRDACFG1_REG | 0x1a005a24:RW |
| GRDACFG2_REG | 0x1a005a28:RW |
| GRDACFG3_REG | 0x1a005a2c:RW |
| GRDACFG4_REG | 0x1a005a30:RW |
| GRDACFG5_REG | 0x1a005a34:RW |
| GRDACFG6_REG | 0x1a005a38:RW |
| GRDACFG7_REG | 0x1a005a3c:RW |
| GRDCFG_REG | 0x1a005a04:RW |
| GRDCS_REG | 0x1a005a00:RW |
| GRFCBA_REG | 0x1a005414:RW |
| GRFCCFG_REG | 0x1a005410:RW |
| GRFCCV0_REG | 0x1a005440:RW |
| GRFCCV1_REG | 0x1a005444:RW |
| GRFCCV2_REG | 0x1a005448:RW |
| GRFCCV3_REG | 0x1a00544c:RW |
| GRFCCV4_REG | 0x1a005450:RW |
| GRFCCV5_REG | 0x1a005454:RW |
| GRFCCV6_REG | 0x1a005458:RW |
| GRFCCV7_REG | 0x1a00545c:RW |
| GRFCFG_REG | 0x1a005404:RW |
| GRFCMSK_REG | 0x1a00542c:RW |
| GRFCSTAT_REG | 0x1a005500:RW |
| GRFCS_REG | 0x1a005400:RW |
| GRFDIMS_REG | 0x1a00540c:RW |
| GRFEBA_REG | 0x1a005434:RW |
| GRFECFG_REG | 0x1a005430:RW |
| GRFSCV_REG | 0x1a005428:RW |
| GRFTLOC_REG | 0x1a005408:RW |
| GRFZBA_REG | 0x1a005420:RW |
| GRFZCFG_REG | 0x1a00541c:RW |
| GRFZCV_REG | 0x1a005424:RW |
| GRMCCT_REG | 0x1a005c28:RW |
| GRMCFG_REG | 0x1a005c04:RW |
| GRMCIH0_REG | 0x1a005cc0:RW |
| GRMCIH1_REG | 0x1a005ce0:RW |
| GRMCIL0_REG | 0x1a005c80:RW |
| GRMCIL1_REG | 0x1a005ca0:RW |
| GRMCS_REG | 0x1a005c00:RW |
| GRMMCT_REG | 0x1a005c1c:RW |
| GRMOADR_REG | 0x1a005c14:RW |
| GRMOCT_REG | 0x1a005c18:RW |
| GRMSADR_REG | 0x1a005c0c:RW |
| GRMSCT_REG | 0x1a005c10:RW |
| GRMSSI0_REG | 0x1a005c20:RW |
| GRMSSI1_REG | 0x1a005c24:RW |
| GRMSVI_REG | 0x1a005c08:RW |
| GROCFG_REG | 0x1a005004:RW |
| GROCS_REG | 0x1A005000:RW |
| GRODBGA_REG | 0x1a005100:RW |
| GROIDC_REG | 0x1a005008:RW |
| GROPCTR0_REG | 0x1a005180:RW |
| GROPCTR10_REG | 0x1a0051d0:RW |
| GROPCTR11_REG | 0x1a0051d8:RW |
| GROPCTR1_REG | 0x1a005188:RW |
| GROPCTR2_REG | 0x1a005190:RW |
| GROPCTR3_REG | 0x1a005198:RW |
| GROPCTR4_REG | 0x1a0051a0:RW |
| GROPCTR5_REG | 0x1a0051a8:RW |
| GROPCTR6_REG | 0x1a0051b0:RW |
| GROPCTR7_REG | 0x1a0051b8:RW |
| GROPCTR8_REG | 0x1a0051c0:RW |
| GROPCTR9_REG | 0x1a0051c8:RW |
| GROPCTRC_REG | 0x1a005170:RW |
| GROPCTRE_REG | 0x1a005174:RW |
| GROPCTRS0_REG | 0x1a005184:RW |
| GROPCTRS10_REG | 0x1a0051d4:RW |
| GROPCTRS11_REG | 0x1a0051dc:RW |
| GROPCTRS1_REG | 0x1a00518c:RW |
| GROPCTRS2_REG | 0x1a005194:RW |
| GROPCTRS3_REG | 0x1a00519c:RW |
| GROPCTRS4_REG | 0x1a0051a4:RW |
| GROPCTRS5_REG | 0x1a0051ac:RW |
| GROPCTRS6_REG | 0x1a0051b4:RW |
| GROPCTRS7_REG | 0x1a0051bc:RW |
| GROPCTRS8_REG | 0x1a0051c4:RW |
| GROPCTRS9_REG | 0x1a0051cc:RW |
| GROPCTR_FBC_CZ_CLRFLG_FETCHES | 0x22 |
| GROPCTR_FBC_CZ_EVICTIONS | 0x31 |
| GROPCTR_FBC_CZ_FETCHES | 0x30 |
| GROPCTR_FBC_CZ_FETCH_STALLS | 0x28 |
| GROPCTR_FBC_CZ_FE_DISCARDED | 0x2E |
| GROPCTR_FBC_CZ_FE_HITS | 0x2D |
| GROPCTR_FBC_CZ_FE_LINE_REQS | 0x2A |
| GROPCTR_FBC_CZ_FE_MISSES | 0x2C |
| GROPCTR_FBC_CZ_FE_QUAD_REQS | 0x29 |
| GROPCTR_FBC_CZ_FE_UNUSED | 0x2B |
| GROPCTR_FBC_CZ_LINE_FLUSHES | 0x23 |
| GROPCTR_FBC_CZ_PBE_HITS | 0x27 |
| GROPCTR_FBC_CZ_PBE_MISSES | 0x26 |
| GROPCTR_FBC_CZ_PBE_REQS | 0x24 |
| GROPCTR_FBC_CZ_PBE_STALLS | 0x25 |
| GROPCTR_FBC_CZ_UM_STALLS | 0x2F |
| GROPCTR_FBC_EZ_CLRFLG_FETCHES | 0x32 |
| GROPCTR_FBC_EZ_EVICTIONS | 0x3F |
| GROPCTR_FBC_EZ_FETCHES | 0x3E |
| GROPCTR_FBC_EZ_FETCH_STALLS | 0x38 |
| GROPCTR_FBC_EZ_FE_FETCHES | 0x3C |
| GROPCTR_FBC_EZ_FE_HITS | 0x3B |
| GROPCTR_FBC_EZ_FE_MISSES | 0x3A |
| GROPCTR_FBC_EZ_FE_REQS | 0x39 |
| GROPCTR_FBC_EZ_LINE_FLUSHES | 0x33 |
| GROPCTR_FBC_EZ_PBE_HITS | 0x37 |
| GROPCTR_FBC_EZ_PBE_MISSES | 0x36 |
| GROPCTR_FBC_EZ_PBE_REQS | 0x34 |
| GROPCTR_FBC_EZ_PBE_STALLS | 0x35 |
| GROPCTR_FBC_EZ_UM_STALLS | 0x3D |
| GROPCTR_FEINVALIDPIXELS | 0x08 |
| GROPCTR_FEPEZIDLE | 0x0A |
| GROPCTR_FEPEZRDY | 0x09 |
| GROPCTR_FESPMRDY | 0x0C |
| GROPCTR_FESPMSTALL | 0x0D |
| GROPCTR_FESTALLPREFETCH | 0x0B |
| GROPCTR_FEVALIDPRIMS | 0x05 |
| GROPCTR_FEVALIDQUADS | 0x07 |
| GROPCTR_FEZCULLEDQUADS | 0x06 |
| GROPCTR_FOVCLIPPEDPRIMS | 0x02 |
| GROPCTR_FOVCULLEDPRIMS | 0x01 |
| GROPCTR_NOFEPIXELPRIMS | 0x04 |
| GROPCTR_PBE_DEPTH_TEST_FAIL | 0x1F |
| GROPCTR_PBE_DPTH_STCL_PASS | 0x21 |
| GROPCTR_PBE_FE_STALLS | 0x1E |
| GROPCTR_PBE_STCL_TEST_FAIL | 0x20 |
| GROPCTR_REVCULLEDPRIMS | 0x03 |
| GROPCTR_TU0_AXI_REQ_FIFO_FULL | 0x10 |
| GROPCTR_TU0_CACHE_ACCESSES | 0x11 |
| GROPCTR_TU0_CACHE_MISSES | 0x14 |
| GROPCTR_TU0_CACHE_RCV_WAITS | 0x15 |
| GROPCTR_TU0_CACHE_REQ_STALLS | 0x13 |
| GROPCTR_TU0_CACHE_STALLS | 0x12 |
| GROPCTR_TU0_SAME_BANK_STALL | 0x0F |
| GROPCTR_TU0_SAME_SET_STALL | 0x0E |
| GROPCTR_TU1_AXI_REQ_FIFO_FULL | 0x18 |
| GROPCTR_TU1_CACHE_ACCESSES | 0x19 |
| GROPCTR_TU1_CACHE_MISSES | 0x1C |
| GROPCTR_TU1_CACHE_RCV_WAITS | 0x1D |
| GROPCTR_TU1_CACHE_REQ_STALLS | 0x1B |
| GROPCTR_TU1_CACHE_STALLS | 0x1A |
| GROPCTR_TU1_SAME_BANK_STALL | 0x17 |
| GROPCTR_TU1_SAME_SET_STALL | 0x16 |
| GRPABS_REG | 0x1a005660:RW |
| GRPBCC_REG | 0x1a005654:RW |
| GRPBCFG_REG | 0x1a005650:RW |
| GRPCBS_REG | 0x1a00565c:RW |
| GRPCDSM_REG | 0x1a005658:RW |
| GRPCFG_REG | 0x1a005604:RW |
| GRPCLSZ_REG | 0x1a00560c:RW |
| GRPCLXY_REG | 0x1a005608:RW |
| GRPCS_REG | 0x1a005600:RW |
| GRPCZSM_REG | 0x1a005658:RW |
| GRPFCOL_REG | 0x1a005664:RW |
| GRPSBCG_REG | 0x1a005648:RW |
| GRPSCC_REG | 0x1a00564c:RW |
| GRPSFCG_REG | 0x1a005644:RW |
| GRPVORG_REG | 0x1a005610:RW |
| GRPZBCG_REG | 0x1a005640:RW |
| GRP_FDBGB_REG | 0x1a005744:RW |
| GRP_FDBGO_REG | 0x1a005740:RW |
| GRP_FDBGR_REG | 0x1a005748:RW |
| GRP_FDBGS_REG | 0x1a00574c:RW |
| GRP_SDBG0_REG | 0x1a005750:RW |
| GRSAADR_REG | 0x1a00581c:RW |
| GRSACT_REG | 0x1a005820:RW |
| GRSCFG_REG | 0x1a005804:RW |
| GRSCS_REG | 0x1a005800:RW |
| GRSDMAX_REG | 0x1a005830:RW |
| GRSDMIN_REG | 0x1a00582c:RW |
| GRSDOF_REG | 0x1a005824:RW |
| GRSDOU_REG | 0x1a005828:RW |
| GRSDZS_REG | 0x1a005840:RW |
| GRSFSF_REG | 0x1a00583c:RW |
| GRSHPX_REG | 0x1a005844:RW |
| GRSLW_REG | 0x1a005838:RW |
| GRSPADR_REG | 0x1a005814:RW |
| GRSPCT_REG | 0x1a005818:RW |
| GRSPSZ_REG | 0x1a005834:RW |
| GRSSP_REG | 0x1a005810:RW |
| GRSVADR_REG | 0x1a005808:RW |
| GRSVFMT_REG | 0x1a00580c:RW |
| GRS_DBGE_REG | 0x1a005900:RW |
| GRTBCOL0_REG | 0x1a00520c:RW |
| GRTBCOL1_REG | 0x1a00522c:RW |
| GRTBCOL2_REG | 0x1a00524c:RW |
| GRTBCOL3_REG | 0x1a00526c:RW |
| GRTBCOL4_REG | 0x1a00528c:RW |
| GRTBCOL5_REG | 0x1a0052ac:RW |
| GRTBCOL6_REG | 0x1a0052cc:RW |
| GRTBCOL7_REG | 0x1a0052ec:RW |
| GRTCDIM0_REG | 0x1a005308:RW |
| GRTCDIM1_REG | 0x1a005388:RW |
| GRTCFG0_REG | 0x1a005204:RW |
| GRTCFG1_REG | 0x1a005224:RW |
| GRTCFG2_REG | 0x1a005244:RW |
| GRTCFG3_REG | 0x1a005264:RW |
| GRTCFG4_REG | 0x1a005284:RW |
| GRTCFG5_REG | 0x1a0052a4:RW |
| GRTCFG6_REG | 0x1a0052c4:RW |
| GRTCFG7_REG | 0x1a0052e4:RW |
| GRTCOFF0_REG | 0x1a005304:RW |
| GRTCOFF1_REG | 0x1a005384:RW |
| GRTCS0_REG | 0x1a005200:RW |
| GRTCS1_REG | 0x1a005280:RW |
| GRTDBG0_REG | 0x1a005300:RW |
| GRTDIM0_REG | 0x1a005208:RW |
| GRTDIM1_REG | 0x1a005228:RW |
| GRTDIM2_REG | 0x1a005248:RW |
| GRTDIM3_REG | 0x1a005268:RW |
| GRTDIM4_REG | 0x1a005288:RW |
| GRTDIM5_REG | 0x1a0052a8:RW |
| GRTDIM6_REG | 0x1a0052c8:RW |
| GRTDIM7_REG | 0x1a0052e8:RW |
| GRTLBIAS0_REG | 0x1a00521c:RW |
| GRTLBIAS1_REG | 0x1a00523c:RW |
| GRTLBIAS2_REG | 0x1a00525c:RW |
| GRTLBIAS3_REG | 0x1a00527c:RW |
| GRTLBIAS4_REG | 0x1a00529c:RW |
| GRTLBIAS5_REG | 0x1a0052bc:RW |
| GRTLBIAS6_REG | 0x1a0052dc:RW |
| GRTLBIAS7_REG | 0x1a0052fc:RW |
| GRTMPM0_BASE | 0x1A005E00 |
| GRTMPM0_REG | 0x1a005e00:RW |
| GRTMPM1_BASE | 0x1A005F00 |
| GRTMPM1_REG | 0x1a005f00:RW |
| GRTMPM_MASK | 0xFFFFFF00 |
| GRTPTBA0_REG | 0x1a005220:RW |
| GRTPTBA1_REG | 0x1a0052a0:RW |
| GRVVSTRD_REG | 0x1a005d00:RW |
| GR_FBC_ADDR_MASK | 0x0000007F |
| GR_FBC_BASE | 0x1A005400 |
| GR_FBC_DEBUG_ADDR_MASK | 0x7F |
| GR_FBC_DEBUG_BASE | 0x1A005500 |
| GR_PPL_ADDR_MASK | 0x0000007F |
| GR_PPL_BASE | 0x1A005600 |
| GR_PPL_DEBUG_ADDR_MASK | 0x0000001F |
| GR_PPL_DEBUG_BASE | 0x1A005740 |
| GR_PSE_ADDR_MASK | 0x0000007f |
| GR_PSE_BASE | 0x1A005800 |
| GR_PSE_DEBUG_ADDR_MASK | 0x00000003 |
| GR_PSE_DEBUG_BASE | 0x1A005900 |
| GR_SYSTEM_BASE | 0x1A005000 |
| GR_SYSTEM_DEBUG_BASE | 0x1A005100 |
| GR_TU_ADDR_MASK | 0x000000FF |
| GR_TU_BASE0 | 0x1A005200 |
| GR_TU_BASE1 | 0x1A005220 |
| GR_TU_BASE2 | 0x1A005240 |
| GR_TU_BASE3 | 0x1A005260 |
| GR_TU_BASE4 | 0x1A005280 |
| GR_TU_BASE5 | 0x1A0052A0 |
| GR_TU_BASE6 | 0x1A0052C0 |
| GR_TU_BASE7 | 0x1A0052E0 |
| GR_TU_DBG_BASE | 0x1A005300 |
| GR_TU_UNIT_MASK | 0xFFFFFF1F |
| GR_UNIFORM_ADDR_MASK | 0x00000fff |
| GR_UNIFORM_BASE | 0x1a00c000 |
| GR_UNIFORM_SIZE | 0x00001000 |
| GR_VCACHE_ADDR_MASK | 0x00001fff |
| GR_VCACHE_BASE | 0x1a00a000 |
| GR_VCACHE_SIZE | 0x00002000 |
| GR_VCD_ADDR_MASK | 0x0000007f |
| GR_VCD_BASE | 0x1A005A00 |
| GR_VCM_ADDR_MASK | 0x0000003f |
| GR_VCM_BASE | 0x1A005C00 |
| GR_VCM_CI_ADDR_MASK | 0x0000007f |
| GR_VCM_CI_BASE | 0x1A005C80 |
| GR_VPM_VRFCFG_ADDR_MASK | 0x00000003 |
| GR_VPM_VRFCFG_BASE | 0x1A005D00 |
| HW_POINTER_TO_ADDRESS(pointer) | MACRO |
| HW_REGISTER_RO(addr) | MACRO |
| HW_REGISTER_RW(addr) | MACRO |
| I1CACHE_BASE_REG | 0xffffffff:RW |
| I2CA_0_REG | 0x7e20500c:RW |
| I2CA_1_REG | 0x7e80400c:RW |
| I2CA_2_REG | 0x7e80500c:RW |
| I2CA_3_REG | I2C_BASE_3 + 0x0C:RW |
| I2CA_REG | 0x7e20500c:RW |
| I2CA_x(x) | MACRO |
| I2CCLKT_0_REG | 0x7e20501c:RW |
| I2CCLKT_1_REG | 0x7e80401c:RW |
| I2CCLKT_2_REG | 0x7e80501c:RW |
| I2CCLKT_3_REG | I2C_BASE_3 + 0x1C:RW |
| I2CCLKT_REG | 0x7e20501c:RW |
| I2CCLKT_x(x) | MACRO |
| I2CC_0_REG | 0x7e205000:RW |
| I2CC_1_REG | 0x7e804000:RW |
| I2CC_2_REG | 0x7e805000:RW |
| I2CC_3_REG | I2C_BASE_3 + 0x00:RW |
| I2CC_CLEAR | 48 |
| I2CC_EN | 0x8000 |
| I2CC_INTD | 256 |
| I2CC_INTR | 0x400 |
| I2CC_INTT | 0x200 |
| I2CC_READ | 1 |
| I2CC_REG | 0x7e205000:RW |
| I2CC_START | 128 |
| I2CC_x(x) | MACRO |
| I2CDEL_0_REG | 0x7e205018:RW |
| I2CDEL_1_REG | 0x7e804018:RW |
| I2CDEL_2_REG | 0x7e805018:RW |
| I2CDEL_3_REG | I2C_BASE_3 + 0x18:RW |
| I2CDEL_FEDL | (16) |
| I2CDEL_REDL | (0) |
| I2CDEL_REG | 0x7e205018:RW |
| I2CDEL_x(x) | MACRO |
| I2CDIV_0_REG | 0x7e205014:RW |
| I2CDIV_1_REG | 0x7e804014:RW |
| I2CDIV_2_REG | 0x7e805014:RW |
| I2CDIV_3_REG | I2C_BASE_3 + 0x14:RW |
| I2CDIV_REG | 0x7e205014:RW |
| I2CDIV_x(x) | MACRO |
| I2CDLEN_0_REG | 0x7e205008:RW |
| I2CDLEN_1_REG | 0x7e804008:RW |
| I2CDLEN_2_REG | 0x7e805008:RW |
| I2CDLEN_3_REG | I2C_BASE_3 + 0x08:RW |
| I2CDLEN_REG | 0x7e205008:RW |
| I2CDLEN_x(x) | MACRO |
| I2CFIFO_0_REG | 0x7e205010:RW |
| I2CFIFO_1_REG | 0x7e804010:RW |
| I2CFIFO_2_REG | 0x7e805010:RW |
| I2CFIFO_3_REG | I2C_BASE_3 + 0x10:RW |
| I2CFIFO_REG | 0x7e205010:RW |
| I2CFIFO_x(x) | MACRO |
| I2CS_0_REG | 0x7e205004:RW |
| I2CS_1_REG | 0x7e804004:RW |
| I2CS_2_REG | 0x7e805004:RW |
| I2CS_3_REG | I2C_BASE_3 + 0x04:RW |
| I2CS_CLKT | 0x200 |
| I2CS_DONE | 2 |
| I2CS_ERR | 256 |
| I2CS_REG | 0x7e205004:RW |
| I2CS_RXD | 32 |
| I2CS_RXF | 128 |
| I2CS_RXR | 8 |
| I2CS_TA | 1 |
| I2CS_TXD | 16 |
| I2CS_TXE | 64 |
| I2CS_TXW | 4 |
| I2CS_x(x) | MACRO |
| I2C_BASE_0 | 0x7e205000 |
| I2C_BASE_1 | 0x7e804000 |
| I2C_BASE_2 | 0x7e805000 |
| IC0CS_REG | 0x7ee02000:RW |
| IC1CS_REG | 0xffffffff:RW |
| IC1END_REG | 0xffffffff:RW |
| IC1START_REG | 0xffffffff:RW |
| IC_0_REG | 0x7e002000:RW |
| IC_1_REG | 0xffffffff:RW |
| IC_MASK0_REG | 0x7e002010:RW |
| IC_REG | 0x7e002000:RW |
| IC_VADDR_REG | 0x7e002030:RW |
| IDCCFG_REG | 0x10002014:RW |
| IDCCMD_REG | 0x10002010:RW |
| IDCKEYHU_REG | 0x10002008:RW |
| IDCKEYLU_REG | 0x1000200C:RW |
| IDCKSEL_REG | 0x10002018:RW |
| IDCLVWMCU_REG | 0x10002000:RW |
| IDCLVWMC_REG | 0x10002020:RW |
| IDCMDIDU_REG | 0x10002004:RW |
| IDCMDID_REG | 0x10002024:RW |
| IFORCE0_0_REG | 0x7e002040:RW |
| IFORCE0_1_REG | 0xffffffff:RW |
| IFORCE1_0_REG | 0x7e002044:RW |
| IFORCE1_1_REG | 0xffffffff:RW |
| IMASK0_0_REG | 0x7e002010:RW |
| IMASK0_1_REG | 0xffffffff:RW |
| IMASK0_REG | 0x7e002010:RW |
| IMASK1_0_REG | 0x7e002014:RW |
| IMASK1_1_REG | 0xffffffff:RW |
| IMASK1_REG | 0x7e002014:RW |
| IMASK2_0_REG | 0x7e002018:RW |
| IMASK2_1_REG | 0xffffffff:RW |
| IMASK2_REG | 0x7e002018:RW |
| IMASK3_0_REG | 0x7e00201c:RW |
| IMASK3_1_REG | 0xffffffff:RW |
| IMASK3_REG | 0x7e00201c:RW |
| IMASK4_0_REG | 0x7e002020:RW |
| IMASK4_1_REG | 0xffffffff:RW |
| IMASK5_0_REG | 0x7e002024:RW |
| IMASK5_1_REG | 0xffffffff:RW |
| IMASK6_0_REG | 0x7e002028:RW |
| IMASK6_1_REG | 0xffffffff:RW |
| IMASK7_0_REG | 0x7e00202c:RW |
| IMASK7_1_REG | 0xffffffff:RW |
| IMASKx_0(x) | MACRO |
| IMASKx_1(x) | MACRO |
| INTERRUPT_3D | 74 |
| INTERRUPT_ADC | 122 |
| INTERRUPT_ARM | 94 |
| INTERRUPT_ASDIO | 126 |
| INTERRUPT_AUXIO | 93 |
| INTERRUPT_AVE | 101 |
| INTERRUPT_AVSPMON | 127 |
| INTERRUPT_CAM0 | 102 |
| INTERRUPT_CAM1 | 103 |
| INTERRUPT_CCP2 | 102 |
| INTERRUPT_CCP2TX | 98 |
| INTERRUPT_CDP | 110 |
| INTERRUPT_CODEC0 | 68 |
| INTERRUPT_CODEC1 | 69 |
| INTERRUPT_CODEC2 | 70 |
| INTERRUPT_CPG | 124 |
| INTERRUPT_CPR | 111 |
| INTERRUPT_CRYPTO | 98 |
| INTERRUPT_CSI2 | 103 |
| INTERRUPT_DMA0 | 80 |
| INTERRUPT_DMA1 | 81 |
| INTERRUPT_DMA10 | 90 |
| INTERRUPT_DMA11 | 91 |
| INTERRUPT_DMA11_12_13_14 | 91 |
| INTERRUPT_DMA12 | 92 |
| INTERRUPT_DMA13 | 93 |
| INTERRUPT_DMA14 | 94 |
| INTERRUPT_DMA15 | 95 |
| INTERRUPT_DMA2 | 82 |
| INTERRUPT_DMA3 | 83 |
| INTERRUPT_DMA4 | 84 |
| INTERRUPT_DMA5 | 85 |
| INTERRUPT_DMA6 | 86 |
| INTERRUPT_DMA7 | 87 |
| INTERRUPT_DMA8 | 88 |
| INTERRUPT_DMA9 | 89 |
| INTERRUPT_DMA_ALL | 92 |
| INTERRUPT_DMA_VPU | 95 |
| INTERRUPT_DSI0 | 100 |
| INTERRUPT_DSI1 | 108 |
| INTERRUPT_DUMMY | 127 |
| INTERRUPT_EXCEPTION_NUM | 32 |
| INTERRUPT_EXCEPTION_OFFSET | 0 |
| INTERRUPT_GPIO0 | 112 |
| INTERRUPT_GPIO1 | 113 |
| INTERRUPT_GPIO2 | 114 |
| INTERRUPT_GPIO3 | 116 |
| INTERRUPT_GPION | 115 |
| INTERRUPT_HARDINT_NUM | 64 |
| INTERRUPT_HARDINT_OFFSET | 64 |
| INTERRUPT_HDMI0 | 104 |
| INTERRUPT_HDMI1 | 105 |
| INTERRUPT_HOSTINTERFACE | 96 |
| INTERRUPT_HOSTPORT | 96 |
| INTERRUPT_HW_NUM | (64) |
| INTERRUPT_HW_OFFSET | (64) |
| INTERRUPT_I2C | 117 |
| INTERRUPT_I2C_SLV | 107 |
| INTERRUPT_I2SPCM | 119 |
| INTERRUPT_ISP | 72 |
| INTERRUPT_JPEG | 71 |
| INTERRUPT_MULTICORESYNC0 | 76 |
| INTERRUPT_MULTICORESYNC1 | 77 |
| INTERRUPT_MULTICORESYNC2 | 78 |
| INTERRUPT_MULTICORESYNC3 | 79 |
| INTERRUPT_PARALLELCAMERA | 107 |
| INTERRUPT_PIXELVALVE0 | 108 |
| INTERRUPT_PIXELVALVE1 | 106 |
| INTERRUPT_PLL | 109 |
| INTERRUPT_PWA0 | 109 |
| INTERRUPT_PWA1 | 110 |
| INTERRUPT_RNG | 125 |
| INTERRUPT_SDC | 99 |
| INTERRUPT_SDCARDHOST | 120 |
| INTERRUPT_SDIO | 120 |
| INTERRUPT_SLIMBUS | 116 |
| INTERRUPT_SMI | 111 |
| INTERRUPT_SOFTINT_NUM | 32 |
| INTERRUPT_SOFTINT_OFFSET | 32 |
| INTERRUPT_SPARE1 | 99 |
| INTERRUPT_SPARE2 | 124 |
| INTERRUPT_SPARE3 | 125 |
| INTERRUPT_SPARE4 | 126 |
| INTERRUPT_SPARE5 | 127 |
| INTERRUPT_SPI | 118 |
| INTERRUPT_SW_NUM | (32) |
| INTERRUPT_SW_OFFSET | (32) |
| INTERRUPT_TIMER0 | 64 |
| INTERRUPT_TIMER1 | 65 |
| INTERRUPT_TIMER2 | 66 |
| INTERRUPT_TIMER3 | 67 |
| INTERRUPT_TRANSPOSER | 75 |
| INTERRUPT_UART | 121 |
| INTERRUPT_UART_SPI0_SPI1 | 93 |
| INTERRUPT_USB | 73 |
| INTERRUPT_VEC | 123 |
| INTERRUPT_VECTOR_BASE | 0 |
| INTERRUPT_VIDEOSCALER | 97 |
| INT_CTL_BASE_ADDR1_REG | 0xffffffff:RW |
| IPROFILE_0_REG | 0x7e002038:RW |
| IPROFILE_1_REG | 0xffffffff:RW |
| ISRC0_0_REG | 0x7e002008:RO |
| ISRC0_1_REG | 0xffffffff:RW |
| ISRC1_0_REG | 0x7e00200c:RO |
| ISRC1_1_REG | 0xffffffff:RW |
| ISRC_REG | 0x7e002008:RO |
| IS_0_REG | 0x7e002004:RO |
| IS_1_REG | 0xffffffff:RW |
| IS_ALIAS_COHERENT(x) | MACRO |
| IS_ALIAS_DIRECT(x) | MACRO |
| IS_ALIAS_L1L2_NONALLOCATING(x) | MACRO |
| IS_ALIAS_L1_NONALLOCATING(x) | MACRO |
| IS_ALIAS_NONALLOCATING(x) | MACRO |
| IS_ALIAS_NORMAL(x) | MACRO |
| IS_ALIAS_NOT_L1(p) | MACRO |
| IS_ALIAS_PERIPHERAL(x) | MACRO |
| IS_ALIAS_STREAMING(x) | MACRO |
| IS_REG | 0x7e002004:RO |
| IVADDR_0_REG | 0x7e002030:RW |
| IVADDR_1_REG | 0xffffffff:RW |
| IWAKEUP_0_REG | 0x7e002034:RW |
| IWAKEUP_1_REG | 0xffffffff:RW |
| JC0BA_REG | 0x7e00504c:RW |
| JC0S_REG | 0x7e005058:RW |
| JC0W_REG | 0x7e005064:RW |
| JC1BA_REG | 0x7e005050:RW |
| JC1S_REG | 0x7e00505c:RW |
| JC1W_REG | 0x7e005068:RW |
| JC2BA_REG | 0x7e005054:RW |
| JC2S_REG | 0x7e005060:RW |
| JC2W_REG | 0x7e00506c:RW |
| JCBA_REG | 0x7e005010:RW |
| JCTRL_DCTEN | 16 |
| JCTRL_FLUSH | 4 |
| JCTRL_MODE | 1 |
| JCTRL_REG | 0x7e005000:RW |
| JCTRL_RESET | 8 |
| JCTRL_START | 128 |
| JCTRL_STUFF | 2 |
| JDCCTRL_DCCOMP_MASK | 0xFFFF |
| JDCCTRL_DISDC | 0x100000 |
| JDCCTRL_REG | 0x7e00500c:RW |
| JDCCTRL_SETDC(n) | MACRO |
| JHADDR_REG | 0x7e005028:RW |
| JHADDR_TABLEF | 0x80000000 |
| JHWDATA_REG | 0x7e00502c:RW |
| JICST_CDONE | 0x10000 |
| JICST_ERR | 0x80000 |
| JICST_INTCD | 1 |
| JICST_INTE | 8 |
| JICST_INTM | 4 |
| JICST_INTSD | 2 |
| JICST_MARKER | 0x40000 |
| JICST_REG | 0x7e005004:RW |
| JICST_SDONE | 0x20000 |
| JMADDR_REG | 0x7e005030:RW |
| JMCTRL_420_MODE | 0 |
| JMCTRL_422_MODE | 0x4000 |
| JMCTRL_444_MODE | 0x8000 |
| JMCTRL_AC_TAB(n) | MACRO |
| JMCTRL_CMP(n) | MACRO |
| JMCTRL_DC_TAB(n) | MACRO |
| JMCTRL_NUMCMP | 256 |
| JMCTRL_REG | 0x7e005008:RW |
| JMCTRL_UNUSED_BITS | 0xf800 |
| JMOP_REG | 0x7e005024:RW |
| JMWDATA_REG | 0x7e005034:RW |
| JNCB_REG | 0x7e005014:RW |
| JNSB_REG | 0x7e00501c:RW |
| JOADDR_REG | 0x7e005038:RW |
| JOWDATA_REG | 0x7e00503c:RW |
| JQADDR_REG | 0x7e005040:RW |
| JQCTRL_REG | 0x7e005048:RW |
| JQWDATA_REG | 0x7e005044:RW |
| JSBO_REG | 0x7e005020:RW |
| JSDA_REG | 0x7e005018:RW |
| L2CACHE_SIZE | (1024 * 128) |
| L2CS_REG | 0x7ee01000:RW |
| L2END_REG | 0x7ee01008:RW |
| L2START_REG | 0x7ee01004:RW |
| MAX_DMA_NUM | 8 |
| MAX_DMA_SUB | 1 |
| MAX_EXCEPTION_NUM | 8 |
| MAX_GPIO_NUM | 2 |
| MAX_TIMER_NUM | 4 |
| MULTICORE_SYNC_ICCLR_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x98:RW |
| MULTICORE_SYNC_ICCLR_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x9C:RW |
| MULTICORE_SYNC_ICSET_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x90:RW |
| MULTICORE_SYNC_ICSET_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x94:RW |
| MULTICORE_SYNC_IREQ_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x84:RW |
| MULTICORE_SYNC_IREQ_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x88:RW |
| MULTICORE_SYNC_MBOX_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xA0:RW |
| MULTICORE_SYNC_MBOX_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xA4:RW |
| MULTICORE_SYNC_MBOX_2_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xA8:RW |
| MULTICORE_SYNC_MBOX_3_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xAC:RW |
| MULTICORE_SYNC_MBOX_4_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xB0:RW |
| MULTICORE_SYNC_MBOX_5_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xB4:RW |
| MULTICORE_SYNC_MBOX_6_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xB8:RW |
| MULTICORE_SYNC_MBOX_7_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xBC:RW |
| MULTICORE_SYNC_MBOX_MASK(num) | MACRO |
| MULTICORE_SYNC_NUM_SEMAPHORES | (32) |
| MULTICORE_SYNC_SEMA_MASK(num) | MACRO |
| MULTICORE_SYNC_SEMA_MASK_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x00:RW |
| MULTICORE_SYNC_SEMA_MASK_10_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x28:RW |
| MULTICORE_SYNC_SEMA_MASK_11_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x2C:RW |
| MULTICORE_SYNC_SEMA_MASK_12_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x30:RW |
| MULTICORE_SYNC_SEMA_MASK_13_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x34:RW |
| MULTICORE_SYNC_SEMA_MASK_14_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x38:RW |
| MULTICORE_SYNC_SEMA_MASK_15_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x3C:RW |
| MULTICORE_SYNC_SEMA_MASK_16_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x40:RW |
| MULTICORE_SYNC_SEMA_MASK_17_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x44:RW |
| MULTICORE_SYNC_SEMA_MASK_18_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x48:RW |
| MULTICORE_SYNC_SEMA_MASK_19_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x4C:RW |
| MULTICORE_SYNC_SEMA_MASK_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x04:RW |
| MULTICORE_SYNC_SEMA_MASK_20_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x50:RW |
| MULTICORE_SYNC_SEMA_MASK_21_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x54:RW |
| MULTICORE_SYNC_SEMA_MASK_22_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x58:RW |
| MULTICORE_SYNC_SEMA_MASK_23_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x5C:RW |
| MULTICORE_SYNC_SEMA_MASK_24_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x60:RW |
| MULTICORE_SYNC_SEMA_MASK_25_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x64:RW |
| MULTICORE_SYNC_SEMA_MASK_26_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x68:RW |
| MULTICORE_SYNC_SEMA_MASK_27_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x6C:RW |
| MULTICORE_SYNC_SEMA_MASK_28_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x70:RW |
| MULTICORE_SYNC_SEMA_MASK_29_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x74:RW |
| MULTICORE_SYNC_SEMA_MASK_2_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x08:RW |
| MULTICORE_SYNC_SEMA_MASK_30_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x78:RW |
| MULTICORE_SYNC_SEMA_MASK_31_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x7C:RW |
| MULTICORE_SYNC_SEMA_MASK_3_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x0C:RW |
| MULTICORE_SYNC_SEMA_MASK_4_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x10:RW |
| MULTICORE_SYNC_SEMA_MASK_5_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x14:RW |
| MULTICORE_SYNC_SEMA_MASK_6_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x18:RW |
| MULTICORE_SYNC_SEMA_MASK_7_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x1C:RW |
| MULTICORE_SYNC_SEMA_MASK_8_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x20:RW |
| MULTICORE_SYNC_SEMA_MASK_9_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x24:RW |
| MULTICORE_SYNC_SEMA_STATUS_REG | MULTICORE_SYNC_BASE_ADDRESS + 0x80:RW |
| MULTICORE_SYNC_VPU_SEMA_0_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xC0:RW |
| MULTICORE_SYNC_VPU_SEMA_1_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xC4:RW |
| MULTICORE_SYNC_VPU_SEMA_STATUS_REG | MULTICORE_SYNC_BASE_ADDRESS + 0xC8:RW |
| MULTICORE_SYNC_VPU_SEMA_x(x) | MACRO |
| NIOREQ_REG | 0x7e008000:RW |
| NOWNT_REG | 0x7e008004:RW |
| PCMCS_DMAEN | 0x200 |
| PCMCS_EN | 1 |
| PCMCS_INTE | 0x1000 |
| PCMCS_INTR | 0x800 |
| PCMCS_INTT | 0x400 |
| PCMCS_REG | PCM_BASE_ADDRESS + 0x00:RW |
| PCMCS_RXCLR | 16 |
| PCMCS_RXD | 0x100000 |
| PCMCS_RXERR | 0x10000 |
| PCMCS_RXF | 0x400000 |
| PCMCS_RXON | 2 |
| PCMCS_RXR | 0x40000 |
| PCMCS_RXSEX | 0x800000 |
| PCMCS_RXSYNC | 0x4000 |
| PCMCS_RXTHR_1_QUARTER | 128 |
| PCMCS_RXTHR_3_QUARTER | 256 |
| PCMCS_RXTHR_EMPTY | 0 |
| PCMCS_RXTHR_FULL | 0x180 |
| PCMCS_RXTHR_LSB | 7 |
| PCMCS_SYNC | 0x1000000 |
| PCMCS_TXCLR | 8 |
| PCMCS_TXD | 0x80000 |
| PCMCS_TXE | 0x200000 |
| PCMCS_TXERR | 0x8000 |
| PCMCS_TXON | 4 |
| PCMCS_TXSYNC | 0x2000 |
| PCMCS_TXTHR_1_QUARTER | 32 |
| PCMCS_TXTHR_3_QUARTER | 64 |
| PCMCS_TXTHR_EMPTY | 0 |
| PCMCS_TXTHR_FULL | 96 |
| PCMCS_TXTHR_LSB | 5 |
| PCMCS_TXW | 0x20000 |
| PCMDREQ_REG | PCM_BASE_ADDRESS + 0x14:RW |
| PCMDREQ_RXDREQTHR_LSB | 0 |
| PCMDREQ_RXPANICTHR_LSB | 16 |
| PCMDREQ_TXDREQTHR_LSB | 8 |
| PCMDREQ_TXPANICTHR_LSB | 24 |
| PCMFIFO_REG | PCM_BASE_ADDRESS + 0x04:RW |
| PCMINTEN_REG | 0x7e203018:RW |
| PCMINTSTC_REG | 0x7e20301c:RW |
| PCMMODE_CLKI | 0x400000 |
| PCMMODE_CLKM | 0x800000 |
| PCMMODE_FLEN | 10 |
| PCMMODE_FRXP | 0x2000000 |
| PCMMODE_FSI | 0x100000 |
| PCMMODE_FSLEN | 0 |
| PCMMODE_FSM | 0x200000 |
| PCMMODE_FTXP | 0x1000000 |
| PCMMODE_PDMRX | 0x4000000 |
| PCMMODE_PDMRXN | 0x8000000 |
| PCMMODE_REG | PCM_BASE_ADDRESS + 0x08:RW |
| PCMRXC_REG | PCM_BASE_ADDRESS + 0x0C:RW |
| PCMTXC_REG | PCM_BASE_ADDRESS + 0x10:RW |
| PERFMON_BASE_ADDRESS | 0x7e20d000 |
| PIXELVALVE_0_BASE_ADDRESS | 0x7e206000 |
| PIXELVALVE_1_BASE_ADDRESS | 0x7e207000 |
| PIXELVALVE_2_BASE_ADDRESS | 0x7e807000 |
| PIXELVALVE_C_0_REG | 0x7e206000:RW |
| PIXELVALVE_C_1_REG | 0x7e207000:RW |
| PIXELVALVE_C_x(x) | MACRO |
| PIXELVALVE_HSYNC_0 | PIXELVALVE0_HSYNC |
| PIXELVALVE_HSYNC_1 | PIXELVALVE1_HSYNC |
| PIXELVALVE_HSYNC_x(x) | MACRO |
| PIXELVALVE_INTEN_0_REG | 0x7e206024:RW |
| PIXELVALVE_INTEN_1_REG | 0x7e207024:RW |
| PIXELVALVE_INTEN_x(x) | MACRO |
| PIXELVALVE_INTSTAT_0_REG | 0x7e206028:RW |
| PIXELVALVE_INTSTAT_1_REG | 0x7e207028:RW |
| PIXELVALVE_INTSTAT_x(x) | MACRO |
| PIXELVALVE_STAT_0_REG | 0x7e20602c:RW |
| PIXELVALVE_STAT_1_REG | 0x7e20702c:RW |
| PIXELVALVE_STAT_x(x) | MACRO |
| PIXELVALVE_VC_0_REG | 0x7e206004:RW |
| PIXELVALVE_VC_1_REG | 0x7e207004:RW |
| PIXELVALVE_VC_x(x) | MACRO |
| PIXELVALVE_VSIZE_0 | PIXELVALVE0_VSIZE |
| PIXELVALVE_VSIZE_1 | PIXELVALVE1_VSIZE |
| PIXELVALVE_VSIZE_x(x) | MACRO |
| PIXELVALVE_VSYNC_0 | PIXELVALVE0_VSYNC |
| PIXELVALVE_VSYNC_1 | PIXELVALVE1_VSYNC |
| PIXELVALVE_VSYNC_x(x) | MACRO |
| POWERMAN_BASE_ADDRESS | 0x7e100000 |
| PRMCS_REG | 0x7e20d000:RW |
| PRMCV_REG | 0x7e20d004:RW |
| PRMSCC_REG | 0x7e20d008:RW |
| PWMCTL_CLRF1 | 6 |
| PWMCTL_MODE(n) | MACRO |
| PWMCTL_MODE1 | 1 |
| PWMCTL_MODE2 | 9 |
| PWMCTL_MODE3 | 17 |
| PWMCTL_MODE4 | 25 |
| PWMCTL_MSEN(n) | MACRO |
| PWMCTL_MSEN1 | 7 |
| PWMCTL_MSEN2 | 15 |
| PWMCTL_MSEN3 | 23 |
| PWMCTL_MSEN4 | 31 |
| PWMCTL_POLA(n) | MACRO |
| PWMCTL_POLA1 | 4 |
| PWMCTL_POLA2 | 12 |
| PWMCTL_POLA3 | 20 |
| PWMCTL_POLA4 | 28 |
| PWMCTL_PWEN(n) | MACRO |
| PWMCTL_PWEN1 | 0 |
| PWMCTL_PWEN2 | 8 |
| PWMCTL_PWEN3 | 16 |
| PWMCTL_PWEN4 | 24 |
| PWMCTL_REG | 0x7e20c000:RW |
| PWMCTL_RPTL(n) | MACRO |
| PWMCTL_RPTL1 | 2 |
| PWMCTL_RPTL2 | 10 |
| PWMCTL_RPTL3 | 18 |
| PWMCTL_RPTL4 | 26 |
| PWMCTL_SBIT(n) | MACRO |
| PWMCTL_SBIT1 | 3 |
| PWMCTL_SBIT2 | 11 |
| PWMCTL_SBIT3 | 19 |
| PWMCTL_SBIT4 | 27 |
| PWMCTL_USEF(n) | MACRO |
| PWMCTL_USEF1 | 5 |
| PWMCTL_USEF2 | 13 |
| PWMCTL_USEF3 | 21 |
| PWMCTL_USEF4 | 29 |
| PWMDAT1_REG | 0x7e20c014:RW |
| PWMDAT2_REG | 0x7e20c024:RW |
| PWMDAT3_REG | 0x7e20c034:RW |
| PWMDAT4_REG | 0x7e20c044:RW |
| PWMDMAC_DREQ | 0 |
| PWMDMAC_DREQ_LEN | 8 |
| PWMDMAC_ENAB | 31 |
| PWMDMAC_PANIC | 8 |
| PWMDMAC_PANIC_LEN | 8 |
| PWMDMAC_REG | 0x7e20c008:RW |
| PWMFIF1_REG | 0x7e20c018:RW |
| PWMRNG1_REG | 0x7e20c010:RW |
| PWMRNG2_REG | 0x7e20c020:RW |
| PWMRNG3_REG | 0x7e20c030:RW |
| PWMRNG4_REG | 0x7e20c040:RW |
| PWMSTA_BERR | 8 |
| PWMSTA_EMPT1 | 1 |
| PWMSTA_FULL1 | 0 |
| PWMSTA_GAPO1 | 4 |
| PWMSTA_GAPO2 | 5 |
| PWMSTA_GAPO3 | 6 |
| PWMSTA_GAPO4 | 7 |
| PWMSTA_REG | 0x7e20c004:RW |
| PWMSTA_RERR1 | 3 |
| PWMSTA_STA1 | 9 |
| PWMSTA_STA2 | 10 |
| PWMSTA_STA3 | 11 |
| PWMSTA_STA4 | 12 |
| PWMSTA_WERR1 | 2 |
| RESET_CONTROLLER_BASE | RS_BASE |
| RSC0ADDR_REG | RS_BASE + 0x10:RW |
| RSTCS_REG | RS_BASE + 0x0:RW |
| RSTFD_REG | RS_BASE + 0xc:RW |
| RSTID_REG | RS_BASE + 0x8:RW |
| RSTWD_REG | RS_BASE + 0x4:RW |
| RUN_ARBITER_CTRL_BASE_ADDRESS_REG | 0xffffffff:RW |
| SDARG_REG | SDCARD_BASE + 0x04:RW |
| SDCDIV_REG | SDCARD_BASE + 0x0C:RW |
| SDCMD_REG | SDCARD_BASE + 0x00:RW |
| SDCS_REG | 0x7ee00000:RW |
| SDCYC_REG | 0x7ee00030:RO |
| SDDATA_REG | SDCARD_BASE + 0x40:RW |
| SDDAT_REG | 0x7ee00038:RO |
| SDEDM_REG | SDCARD_BASE + 0x34:RW |
| SDHBCT_REG | SDCARD_BASE + 0x3C:RW |
| SDHBLC_REG | SDCARD_BASE + 0x50:RW |
| SDHCFG_REG | SDCARD_BASE + 0x38:RW |
| SDHSTS_REG | SDCARD_BASE + 0x20:RW |
| SDIDL_REG | 0x7ee00018:RW |
| SDRAC_REG | 0x7ee0002c:RO |
| SDRAM_BASE_ADDRESS | 0x7ee00000 |
| SDRAM_CTRL_DMA | 0 |
| SDRAM_SIZE | (1024 * 1024 * 128) |
| SDRAM_START_ADDRESS | 0 |
| SDRDC_REG | 0x7ee00024:RO |
| SDRSP0_REG | SDCARD_BASE + 0x10:RW |
| SDRSP1_REG | SDCARD_BASE + 0x14:RW |
| SDRSP2_REG | SDCARD_BASE + 0x18:RW |
| SDRSP3_REG | SDCARD_BASE + 0x1C:RW |
| SDRTC_REG | 0x7ee0001c:RW |
| SDSA_REG | 0x7ee00004:RW |
| SDSB_REG | 0x7ee00008:RW |
| SDSC_REG | 0x7ee0000c:RW |
| SDSECEND0_REG | 0x7ee00040:RW |
| SDSECEND1_REG | 0x7ee00048:RW |
| SDSECEND2_REG | 0x7ee00050:RW |
| SDSECEND3_REG | 0x7ee00058:RW |
| SDSECSRT0_REG | 0x7ee0003c:RW |
| SDSECSRT1_REG | 0x7ee00044:RW |
| SDSECSRT2_REG | 0x7ee0004c:RW |
| SDSECSRT3_REG | 0x7ee00054:RW |
| SDTMC_REG | 0x7ee0007c:RW |
| SDTOUT_REG | SDCARD_BASE + 0x08:RW |
| SDVDD_REG | SDCARD_BASE + 0x30:RW |
| SDWDC_REG | 0x7ee00028:RO |
| SDWTC_REG | 0x7ee00020:RO |
| SET_GPIO_ALT(g,a) | MACRO |
| SMIA_DEVICE | 8 |
| SMIA_REG | 0x7e600008:RW |
| SMICS_ACTIVE | 2 |
| SMICS_AFERR | 25 |
| SMICS_CLEARFIFO | 4 |
| SMICS_DONE | 1 |
| SMICS_EDREQ | 15 |
| SMICS_ENABLE | 0 |
| SMICS_INTD | 9 |
| SMICS_INTR | 11 |
| SMICS_INTT | 10 |
| SMICS_PAD | 6 |
| SMICS_PVMODE | 12 |
| SMICS_PXLDAT | 14 |
| SMICS_REG | 0x7e600000:RW |
| SMICS_RXD | 29 |
| SMICS_RXF | 31 |
| SMICS_RXR | 27 |
| SMICS_SETERR | 13 |
| SMICS_START | 3 |
| SMICS_TEEN | 8 |
| SMICS_TXD | 28 |
| SMICS_TXE | 30 |
| SMICS_TXW | 26 |
| SMICS_WRITE | 5 |
| SMIDA_DEVICE | 8 |
| SMIDA_REG | 0x7e600038:RW |
| SMIDCS_DONE | 2 |
| SMIDCS_ENABLE | 0 |
| SMIDCS_REG | 0x7e600034:RW |
| SMIDCS_START | 1 |
| SMIDCS_WRITE | 3 |
| SMIDC_DMAEN | 28 |
| SMIDC_DMAP | 24 |
| SMIDC_PANICR | 18 |
| SMIDC_PANICW | 12 |
| SMIDC_REG | 0x7e600030:RW |
| SMIDC_REQR | 6 |
| SMIDC_REQW | 0 |
| SMIDD_REG | 0x7e60003c:RW |
| SMIDSR0_REG | 0x7e600010:RW |
| SMIDSR1_REG | 0x7e600018:RW |
| SMIDSR2_REG | 0x7e600020:RW |
| SMIDSR3_REG | 0x7e600028:RW |
| SMIDSW0_REG | 0x7e600014:RW |
| SMIDSW1_REG | 0x7e60001c:RW |
| SMIDSW2_REG | 0x7e600024:RW |
| SMIDSW3_REG | 0x7e60002c:RW |
| SMIDS_DREQ | 7 |
| SMIDS_FORMAT | 23 |
| SMIDS_FSETUP | 22 |
| SMIDS_HOLD | 16 |
| SMIDS_MODE68 | 23 |
| SMIDS_PACE | 8 |
| SMIDS_PACEALL | 15 |
| SMIDS_SETUP | 24 |
| SMIDS_STROBE | 0 |
| SMIDS_SWAP | 22 |
| SMIDS_WIDTH | 30 |
| SMID_REG | 0x7e60000c:RW |
| SMIFD_FCNT | 0 |
| SMIFD_FLVL | 8 |
| SMIFD_REG | 0x7e600040:RW |
| SMIL_REG | 0x7e600004:RW |
| SPICLK_REG | SPI_BASE_ADDRESS + 0x08:RW |
| SPICS_REG | SPI_BASE_ADDRESS + 0x00:RW |
| SPIDLEN_REG | SPI_BASE_ADDRESS + 0x0C:RW |
| SPIFIFO_REG | SPI_BASE_ADDRESS + 0x04:RW |
| STC0_0_REG | 0x7e00300c:RW |
| STC0_1_REG | 0xffffffff:RW |
| STC0_REG | 0x7e00300c:RW |
| STC0_x(x) | MACRO |
| STC1_0_REG | 0x7e003010:RW |
| STC1_1_REG | 0xffffffff:RW |
| STC1_REG | 0x7e003010:RW |
| STC1_x(x) | MACRO |
| STC2_0_REG | 0x7e003014:RW |
| STC2_1_REG | 0xffffffff:RW |
| STC2_REG | 0x7e003014:RW |
| STC2_x(x) | MACRO |
| STC3_0_REG | 0x7e003018:RW |
| STC3_1_REG | 0xffffffff:RW |
| STC3_REG | 0x7e003018:RW |
| STC3_x(x) | MACRO |
| STCHI_0_REG | 0x7e003008:RO |
| STCHI_1_REG | 0xffffffff:RO |
| STCHI_REG | 0x7e003008:RO |
| STCHI_x(x) | MACRO |
| STCLO_0_REG | 0x7e003004:RO |
| STCLO_1_REG | 0xffffffff:RO |
| STCLO_REG | 0x7e003004:RO |
| STCLO_x(x) | MACRO |
| STCS_0_REG | 0x7e003000:RW |
| STCS_1_REG | 0xffffffff:RW |
| STCS_REG | 0x7e003000:RW |
| STCS_x(x) | MACRO |
| STC_0_REG | 0x7e003004:RO |
| STC_1_REG | 0xffffffff:RO |
| STC_REG | 0x7e003004:RO |
| STC_x(x) | MACRO |
| SYSTEM_TIMER_BASE1_REG | 0xffffffff:RW |
| TE0C_REG | TECTL_BASE_ADDRESS + 0x00:RW |
| TE0_VSWIDTH_REG | TECTL_BASE_ADDRESS + 0x08:RW |
| TE1C_REG | TECTL_BASE_ADDRESS + 0x04:RW |
| TE1_VSWIDTH_REG | TECTL_BASE_ADDRESS + 0x0C:RW |
| TH0CFG_REG | 0x18011004:RW |
| TH0CS_REG | 0x18011000:RW |
| TH0ITPC_REG | 0x1801100c:RW |
| TH0STPC_REG | 0x18011008:RW |
| TH0T0PC_REG | 0x18011010:RW |
| TH0T0UD_REG | 0x18011014:RW |
| TH0T1PC_REG | 0x18011018:RW |
| TH0T1UD_REG | 0x1801101c:RW |
| TH0T2PC_REG | 0x18011020:RW |
| TH0T2UD_REG | 0x18011024:RW |
| TH0T3PC_REG | 0x18011028:RW |
| TH0T3UD_REG | 0x1801102c:RW |
| TH0_ADDR_MASK | 0x0000003F |
| TH0_BASE | 0x18011000 |
| TH1CFG_REG | 0x1a008004:RW |
| TH1CS_REG | 0x1a008000:RW |
| TH1ITPC_REG | 0x1a00800c:RW |
| TH1STPC_REG | 0x1a008008:RW |
| TH1T0PC_REG | 0x1a008010:RW |
| TH1T0UD_REG | 0x1a008014:RW |
| TH1T1PC_REG | 0x1a008018:RW |
| TH1T1UD_REG | 0x1a00801c:RW |
| TH1T2PC_REG | 0x1a008020:RW |
| TH1T2UD_REG | 0x1a008024:RW |
| TH1T3PC_REG | 0x1a008028:RW |
| TH1T3UD_REG | 0x1a00802c:RW |
| TH1_ADDR_MASK | 0x0000003F |
| TH1_BASE | 0x1A008000 |
| TIMER_CTRL_32BIT | 2 |
| TIMER_CTRL_DBGHALT | 256 |
| TIMER_CTRL_DIV1 | 0 |
| TIMER_CTRL_DIV16 | 4 |
| TIMER_CTRL_DIV256 | 8 |
| TIMER_CTRL_ENABLE | 128 |
| TIMER_CTRL_ENAFREE | 0x200 |
| TIMER_CTRL_FREEDIV_MASK | 0xff |
| TIMER_CTRL_FREEDIV_SHIFT | 16) |
| TIMER_CTRL_IE | 32 |
| TIMER_CTRL_ONESHOT | 1 |
| TIMER_CTRL_PERIODIC | 64 |
| TRANSPOSER_BASE_ADDRESS | 0x7e004000 |
| TRANSPOSER_CONTROL_REG | 0x7e00400c:RW |
| TRANSPOSER_DIMENSIONS_REG | 0x7e004008:RW |
| TRANSPOSER_DST_PITCH_REG | 0x7e004004:RW |
| TRANSPOSER_DST_PTR_REG | 0x7e004000:RW |
| TRANSPOSER_PROGRESS_REG | 0x7e004010:RO |
| UDLL_REG | 0x7e201000:RW |
| UDLM_REG | 0x7e201004:RW |
| UEN_REG | 0x7e201020:RW |
| UFCR_REG | 0x7e201008:RW |
| UIER_REG | 0x7e201004:RW |
| UIIR_REG | 0x7e201008:RO |
| ULCR_REG | 0x7e20100c:RW |
| ULSR_REG | 0x7e201014:RW |
| UMCR_REG | 0x7e201010:RW |
| UMSR_REG | 0x7e201018:RW |
| UNICAM_ANA(x) | MACRO |
| UNICAM_CAP0(x) | MACRO |
| UNICAM_CAP1(x) | MACRO |
| UNICAM_CLK(x) | MACRO |
| UNICAM_CLT(x) | MACRO |
| UNICAM_CMP0(x) | MACRO |
| UNICAM_CMP1(x) | MACRO |
| UNICAM_CTRL(x) | MACRO |
| UNICAM_DAT0(x) | MACRO |
| UNICAM_DAT1(x) | MACRO |
| UNICAM_DAT2(x) | MACRO |
| UNICAM_DAT3(x) | MACRO |
| UNICAM_DBCTL(x) | MACRO |
| UNICAM_DBEA0(x) | MACRO |
| UNICAM_DBEA1(x) | MACRO |
| UNICAM_DBSA0(x) | MACRO |
| UNICAM_DBSA1(x) | MACRO |
| UNICAM_DBWP(x) | MACRO |
| UNICAM_DCS(x) | MACRO |
| UNICAM_DLT(x) | MACRO |
| UNICAM_IBEA0(x) | MACRO |
| UNICAM_IBEA1(x) | MACRO |
| UNICAM_IBLS(x) | MACRO |
| UNICAM_IBSA0(x) | MACRO |
| UNICAM_IBSA1(x) | MACRO |
| UNICAM_IBWP(x) | MACRO |
| UNICAM_ICC(x) | MACRO |
| UNICAM_ICS(x) | MACRO |
| UNICAM_ICTL(x) | MACRO |
| UNICAM_IDC(x) | MACRO |
| UNICAM_IDCA(x) | MACRO |
| UNICAM_IDCD(x) | MACRO |
| UNICAM_IDI0(x) | MACRO |
| UNICAM_IDI1(x) | MACRO |
| UNICAM_IDPO(x) | MACRO |
| UNICAM_IDS(x) | MACRO |
| UNICAM_IHSTA(x) | MACRO |
| UNICAM_IHWIN(x) | MACRO |
| UNICAM_IPIPE(x) | MACRO |
| UNICAM_ISTA(x) | MACRO |
| UNICAM_IVSTA(x) | MACRO |
| UNICAM_IVWIN(x) | MACRO |
| UNICAM_MISC(x) | MACRO |
| UNICAM_PRI(x) | MACRO |
| UNICAM_REG(x,d) | MACRO |
| UNICAM_STA(x) | MACRO |
| UNUSED_DMA_12 | 0xc0000 |
| UNUSED_DMA_14 | 0xe0000 |
| URBR_REG | 0x7e201000:RO |
| USCR_REG | 0x7e20101c:RW |
| UTHR_REG | 0x7e201000:RW |
| VCINTMASK0_REG | 0x7f4408b8:RW |
| VCINTMASK1_REG | 0x7f4408c0:RW |
| VCODEC_VERSION | 821 |
| VCSIGNAL0_REG | 0x7f4408b4:RW |
| VCSIGNAL1_REG | 0x7f4408bc:RW |
| VIDEOCODEC_BASE_ADDRESS | 0x7f000000 |
| VIDEOCORE_NUM_CORES | 2 |
| VIDEOCORE_NUM_GPIO_PINS | 70 |
| VIDEOCORE_NUM_UART_PORTS | 1 |
| VIDEO_ENC_PrimaryControl_REG | 0x7e806068:RW |
| VIDEO_ENC_RevID_REG | 0x7e806060:RW |
| VPU0_THREAD_CTRL_BASE_ADDRESS | 0x18011000 |
| VPU1_THREAD_CTRL_BASE_ADDRESS_REG | 0xffffffff:RW |
| VPU1_UNIFORM_MEM_BASE_ADDRESS_REG | 0xffffffff:RW |
| VRF_SIZE | 0x1080 |
| WOGLPTR_REG | 0x1820FFFC:RW |
| WSE_CONTROL_REG | 0x7e8060c4:RW |
| WSE_RESET_REG | 0x7e8060c0:RW |
| WSE_VPS_CONTROL_REG | 0x7e8060d0:RW |
| WSE_VPS_DATA_1_REG | 0x7e8060cc:RW |
| WSE_WSS_DATA_REG | 0x7e8060c8:RW |